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simulation is different register level and gate level

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gepo

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gate level of register

Hi, all
I found a weird problem.
I have a register level verilog file mips.v and a gate level verilog file mips_struct.v which is generated by design compiler of synopsys. A testbench file: mips_test.v
however when I conduct the simulation of mips.v using modelsim. The result is right.
However, when i used the same testbench and the gate level file: mips_struct.v to do the simulation using modelsim. The result is totally different.

Any ideas?

Thanks

Added after 4 minutes:

whethere there is some verification tool to verify different level desings?

Thanks
 

RTL simulation will verify the function of the design while Gate level simulation will verify the timing of the design!
 

There are several possibilities:
First: You rtl code is not in good form for synthesis, which will cause mismatch between rtl code and gate-level code.
Second: There are timing violations.
Third: SDF file is needed by simulation tool.
 

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