emad_vhdl
Newbie level 1
fir cic fpga
Hi All,
I am working on master thesis in SDR based on FPGA.
I have been trying to work out how to design the CIC / FIR filter pair in
the DDC section of this design.
I need a help to understand the main operation of these filters.
Hopefully someone out there will be able to help.
Hi All,
I am working on master thesis in SDR based on FPGA.
I have been trying to work out how to design the CIC / FIR filter pair in
the DDC section of this design.
I need a help to understand the main operation of these filters.
Hopefully someone out there will be able to help.