sjalloq
Newbie level 3
modelsim saif
Hi there,
I've been following the Synopsys Power Compiler UG for SAIF generation using VHDL RTL. However, when I issue the set_toggle_region command ModelSim crashes.
The flow I've been following is:
- read in RTL to dc_shell
- write out a forward-annoted SAIF file for use in ModelSim
- compile the VHDL RTL using vcom
- launch ModelSim linked to the Synopsys DPFLI shared object library
- read in the forward-annoted SAIF file using read_rtl_saif
- try to set the toggle region using the set_toggle_region command
and ModelSim crashes as I issue the set_toggle_region command.
So far my theory on the crash is based on the fact that the forward-annotated SAIF file doesn't match the naming once the design is read into ModelSim. For example, I have generate statements replicating module instances and the way Synopsys and Mentor unroll the generate statements differs. In my forward SAIF file I have u_dut/u_datapath_0, whereas in ModelSim I have u_dut/generate_datapath__0/u_datapath.
Could the crash be caused by the DPFLI getting in a twist trying to annotate the forward SAIF?
Has anyone successfully used the DPFLI flow for VHDL RTL SAIF generation?
Thanks.
Hi there,
I've been following the Synopsys Power Compiler UG for SAIF generation using VHDL RTL. However, when I issue the set_toggle_region command ModelSim crashes.
The flow I've been following is:
- read in RTL to dc_shell
- write out a forward-annoted SAIF file for use in ModelSim
- compile the VHDL RTL using vcom
- launch ModelSim linked to the Synopsys DPFLI shared object library
- read in the forward-annoted SAIF file using read_rtl_saif
- try to set the toggle region using the set_toggle_region command
and ModelSim crashes as I issue the set_toggle_region command.
So far my theory on the crash is based on the fact that the forward-annotated SAIF file doesn't match the naming once the design is read into ModelSim. For example, I have generate statements replicating module instances and the way Synopsys and Mentor unroll the generate statements differs. In my forward SAIF file I have u_dut/u_datapath_0, whereas in ModelSim I have u_dut/generate_datapath__0/u_datapath.
Could the crash be caused by the DPFLI getting in a twist trying to annotate the forward SAIF?
Has anyone successfully used the DPFLI flow for VHDL RTL SAIF generation?
Thanks.