saikat
Member level 2
DDR on ML402 problem
Has anyone been able to get the ML402's DDR SDRAM running with a
MIG-generated DDR controller, as opposed to the EDK PLB/OPB DDR controller? I have generated DDR SDRAM interface core from MIG, but unable to generate bit file with the pin locking as inplemented in the board. DDR_CLK and DDR_CLKn signals are driven through A10 and B10 pins of the FPGA(V4SX35), but ISE9.1 is not allowing to map those signals to the IOBs as OUTPUT signal.
Any help??
Has anyone been able to get the ML402's DDR SDRAM running with a
MIG-generated DDR controller, as opposed to the EDK PLB/OPB DDR controller? I have generated DDR SDRAM interface core from MIG, but unable to generate bit file with the pin locking as inplemented in the board. DDR_CLK and DDR_CLKn signals are driven through A10 and B10 pins of the FPGA(V4SX35), but ISE9.1 is not allowing to map those signals to the IOBs as OUTPUT signal.
Any help??
