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Can we put delay in the RTL for FPGA usage?

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cafukarfoo

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Hi Sir/Madam,

Can we put delay value in the RTL that we want to put inside FPGA for testing?

Is the FPGA synthesis going to honors this delay value?

Thanks in advance for your help.

always @(posedge clk)
val_d <= #1 va;
 

Do you mean like use "wait for 100ns" and then the FPGA translates it into real time delay !!!

Well I'm not sure, but I dought it ...


cafukarfoo said:
Hi Sir/Madam,

Can we put delay value in the RTL that we want to put inside FPGA for testing?

Is the FPGA synthesis going to honors this delay value?

Thanks in advance for your help.

always @(posedge clk)
val_d <= #1 va;
Click to expand...
 

it is possible to add delay; but i don't recommend you
it has no effect; it will affect only in simulation not in the hardware implementation
 

wait statements are not supported by the synthesis tool. I think, depends on the tool, it will report an error.
 

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