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verilog : conditional assign statement

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ashishnetam

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verilog assign

Hi All,

Can I use assign statement in verilog according to any active variable?

For example suppose I want to use assign statement if active( any reg ) is enable (say high active).

assign xyz = abc if (active ) other wise dont execute this statement at all.

Is it possible to do in verilog?


Thanks in advance
Ashish
 

verilog conditional assign

I think the clearest way is to use an if statement in a combinational always block. It infers an asynchronous latch.

Code: 
always @(active, abc)
begin
  if (active) xyz <= abc;
end
The specification of all input signals is needed for correct simulation behaviour.

The below statement should work, too:
Code: 
assign xyz = (active)?abc:xyz;
 

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