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A Question About Delta Sigma Modulators

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naalald

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I have designed a 2nd order delta sigma modulator. In TT 25 corner the SNR is 63.8 dB. The worst result is obtained in the SF 85 which has 33 dB SNR. I want to improve the modulator performance so that it reaches a minimum SNR of 62 dB in all corners.
Is it possible to do this by improving the opamps, that is increasing their gain or bandwidth, or should I do something else?
Any suggestion.
 

could u plz explain more on the architecture u have used. is it SC or CT?, no. of quantizer bits?. is this a post layout simulation? are u considering parasitics also while simulating? wat process and supply voltage u r working on?wat kind of dac are u using in the feedback?plz explain in detail bout it, then someone shud be able to help u out..
 

Hi,
Thanks for your reply.
The details are so:
SC architecture, 1 bit quantizer, No parasitics are considered, process is 0.18 um and the supply voltage is 0.9 V.
Thanks for your suggestions.
 

naalald said:
Hi,
Thanks for your reply.
The details are so:
SC architecture, 1 bit quantizer, No parasitics are considered, process is 0.18 um and the supply voltage is 0.9 V.
Thanks for your suggestions.

Is 0.9V a nominal supply voltage in 0.18um technology?
 

Of course not. The nominal voltage in 0.18 um is 1.8 V. In fact, my design is considered a low voltage design.
 

naalald said:
Of course not. The nominal voltage in 0.18 um is 1.8 V. In fact, my design is considered a low voltage design.

In this case, you better check if your ota can work under the corners you mention with this supply voltage. Also, check your on switch resistance under this low voltage requirement.

I would also check the leakage current under this supply voltage (the reverse bias pn junction is now 0.9V)
 

The OTA works in all corners well enough.
 

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