Minimum Of N Numbers using verilog or VHDL

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-- Engineer: Eng. Mostafa M. Amer
-- 
-- Create Date:    10:28:31 11/17/2008 
-- Design Name: Minimum of N 8-bit unsigned numbers
-- Module Name:    minimum_N - Behavioral 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity minimum_N is
    Port ( NO_IN : in  STD_LOGIC_VECTOR (7 downto 0); 	-- Input stream
			  ENA : in STD_LOGIC;									-- Enable
           CLK : in  STD_LOGIC;									-- Clock
           MIN_OUT : out  STD_LOGIC_VECTOR (7 downto 0));-- The minimum of the stream
end minimum_N;

architecture Behavioral of minimum_N is
	signal min : std_logic_vector(7 downto 0):="11111111"; -- Initial min to the maximum possible number
begin


comparator:
process(CLK)
begin
if (ENA='1') then 
   if (CLK'event and CLK ='1') then   
      if ( NO_IN < min ) then 
			min <= NO_IN;
      else 
         min <= min;
      end if;
   end if; 
else
	min <= min;
end if;
end process; 
    
MIN_OUT <= min;
				

end Behavioral;