Using MIG design for virtex4 DDR2 SDRAM

Hi,
I am a design engineer, i want to use MIG design for virtex4 DDR2 (micron), xilinx provides its MIG controller, i installed MIG v1.72 , and generated a ddr2 sdram controller, with data width 8, with its provided test bench (I used the controller with DCM and Testbench.
when i simulated the design with ModelSim SE6.0a, the “init_done” signal do not active.
The initialization sequence is done (accordingly to XAPP702 of xilinx) .
The calibration procedure begins by the training pattern that is ,a continuously oscillating (1010…)pattern.The controller performs a continuous read from memory. But it is do not never finish !!!!!

So the pattern_compare8 module dose not assert the ‘COMP_DONE’ signal(this signal is always low).
The controller seems to hang or get stuck in the DQ calibration.
Please help me .

xilinx ddr memory fails virtex4

Maybe, there is no delay for the LUTs used to do "DQ calibration" when do RTl sim. So the DQS signal doesn't delayed to the right point.
I think.

virtex 4 + ddr2 + read + problem

I'm not familiar with the Xilinx core, but I would expect that calibration finishes sometimes with either accept or fail. This is the case at least with cores from other vendors. The core manual should state these things.

It may be the case, that you simply didn't wait long enough, DDR2 calibration is a very time consuming action, related to usual simulation time scales. You have time for a coffee (at least one) while the calibration is simulating. Some cores have an option to reduce the calibration to a single bit in simulation, it still takes long.

ddr2 calibration

I used MIG design for virtex4 DDR1 (micron) before. when i simulated the design with ModelSim SE6.0a, it was ok and there was any problem.
But the controller seems to hang or get stuck in the DQ calibration for DDR2.
I wait 400 us for simulation. it is long enough because core manual states the calibration time is about 250us.

ddr2 sdram module virtex4

Hi yasamin ,

i am also got the same but in virtex-5,
the problem is in the memory code (micron memory core ) and there is no problem in RTL genearted by MIG so don't worry
try the same procedure with cypress memory you will get the signal
and you have any further dobut call me 09943589300

regards
venkatesan

virtex 4 sdram c code

Hi
I did not understand your suggested solution!:?:
I only simulated the design with ModelSim (no on hardware). So there are any different between the cypress memory and the micron memory, because I only used the memory model which is generated by MIG.
Has been solved your problem with DDR2? Can you guide me more?
Thanks for regards