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How do you take bulk effect into accout?

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hardings

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bulk effect

Hi,

In SPICE simulation, bulk effect is one issue which can easily be ignored.
How do you include that into your simulation?

B.R.
 

why bulk voltage

If the bulk and source are not connected together, the bulk effect will increase the threshold voltage. This effect should be included in the spice model. You should pay attention to reverse bias the diode associated with source and bulk. In modern process, deep N-well can be used to eliminate bulk effect.
 

modeling current through a bulk resistor

Oh, I am not talking about that.

In simulation, bulk is always connected to a fixed level(gnd for psub),but

exactly the bulk is a distributed resistor network, the voltage of different

distance to the origin will be different.

How do you make the model for this resistor network? LPE can do that?

or just estimate a resistor for different cell connection?

Thanks
 

edaboard spice acout

I think that it should be considered with the current in the bulk. If it is little, the resistance could be canceled.
 

deep nwell + spice what two bulk are there

IMHO, isn't there a parameter to calculate the bulk effect in Ids ?
 

modeling bulk effect

"I think that it should be considered with the current in the bulk. If it is little, the resistance could be canceled."
---Yes ,it's true.Actually,I am trying to solve that problem now. The comparator can't work correctly
with large current flowing through bulk.But in simulation , it is working.
Anyone has suggestions about that?
 

I think that you are talking about the Substrate coupling issues...is it so..
ther are some good tool like substrate strom and medica whcih are used for extraction of the substrate model (all those distributed resistance of substrate)
Once you obtained the model for substrate then by injecting some noise current at certain node we can calculate the effect on our circuit due to substrated coupling.

Amit
 

A rough estimation of the bulk resistance is merely to add a resistor calculated in base to the number of squares between the bulk contact and the transistor gate. Then multiply this number by the bulk resistivity, which is normally given in the model card of your transistor.

I think that this could be accurate to about 20%.
 

My guess is you didn't use enough substrate taps, and since your comparator is rapidly driving one side up and the other side down, you get injection, back bias, and crappy performace. i'd be surprised if it doesn't work at all, but bad performance i'd expect if layout is the problem..


another substrate resistance problem is latchup. as you build up voltage across the substrate, you can begin to turn on parasitic vertical devices. put a parasitic pnp (pmos) near an npn (nmos), and you get a free vertical SCR to click on and crowbar lots of current through your well.. DON'T DO THIS!

If you are worrying about how much voltage you are building up across the distributed substrate resistors, i think you are already in trouble - your layout needs substrate taps within 10-30um of any device (and well taps if you are using a twin-well process). absorb these carriers into metal 1 as quickly as possible, and you will be safer.

FYI - for the 1/2 micron analog process (twin well) that's most popular where I work, NMOS drivers sized 30/0.5 exhibited snapback (also caused by voltage across substrate) at 6v with well taps 20um away and 8v with well taps 5um away.
 

some design kit, like IBM PDK, has supplied a substrate connection model, which is equivalent to a resistor. then your bulk is not connected to the 0 ground directly. The bulk voltage will vary according to the transistor working condition. If you don't have that in your design kit, maybe you can do a layout and use the extracted view to run the simulation.
 

IBSIM3 model do not include substrate resistor network. So you must use LPE tools to take into account the substrate resistor network
 

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