Quartus 2 error (10482): VHDL error at mux_8x8.vhd(71)

I have written a structural code vhdl and tried to compile it. Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity mux_8X8 is
port(A,B: in std_logic_vector(7 downto 0);
start, reset, clk: in std_logic;
result: buffer std_logic_vector(15 downto 0);
leds: out std_logic_vector(1 to 7);
done_flag: out std_logic);
end mux_8X8;

architecture behave of mux_8X8 is
signal aout,bout: std_logic_vector(3 downto 0);
signal sel,shift,count: std_logic_vector(1 downto 0);
signal state_out: std_logic_vector(2 downto 0);
signal clken,regclr:std_logic;
signal product: std_logic_vector(7 downto 0);
signal shift_out,sum: std_logic_vector(15 downto 0);

component adder_16
port(x,y: in std_logic_vector(15 downto 0);
sum: out std_logic_vector(15 downto 0));
end component;

component mux2_to_1
port(A,B: in std_logic_vector(3 downto 0);
sel: in std_logic;
y: out std_logic_vector(3 downto 0));
end component;

component seg_7
port(bcd:in std_logic_vector(2 downto 0);
ledsut std_logic_vector(1 to 7));
end component;

component shifter8_16
port(input:in std_logic_vector(7 downto 0);
cnt:in std_logic_vector(1 downto 0);
result:buffer std_logic_vector(15 downto 0));
end component;

component register_16
port(clk, clr,clken: in std_logic;
D: in std_logic_vector(15 downto 0);
Q: out std_logic_vector(15 downto 0));
end component;

component counter_2
port(clk,clr: in std_logic;
Q: out std_logic_vector(1 downto 0));
end component;

component mult4x4
port
(dataa : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
end component;


component state_machine
port( clk, rst, start: in std_logic;
count: in std_logic_vector(1 downto 0);
in_sel,shift: out std_logic_vector(1 downto 0);
state_out: out std_logic_vector(2 downto 0);
done,clken,regclr: out std_logic);
end component;

begin
Adder: adder_16 port map(x,y,sum);
Mux4A: mux2_to_1 port map(A(3 downto 0), A(7 downto 4), sel(1),aout);
Mux4B: mux2_to_1 port map(B(3 downto 0), B(7 downto 4), sel(0),bout);
Seven: seg_7 port map(state_out,leds);
Shifter1: shifter8_16 port map(product,shift,shift_out);
Reg : register_16 port map(clk,regclr,clken,sum,result);
Counter: counter_2 port map(clk,not(start),count);
Mult4x4_1: mult4x4 port map(aout,bout,product);
Control: state_machine port map(clk, reset,start,count,sel,shift, state_out,done_flag,clken,regclr);
end behave;

compile error:
Error (10482): VHDL error at mux_8x8.vhd(71): object "x" is used but not declared
Error (10482): VHDL error at mux_8x8.vhd(71): object "y" is used but not declared

object std_logic is used but not declared

Hi,


x and y are not signals nor ports of mux_8X8 entity so quartus don't know them...

error 10482

As another suggestion: The positional notation in component instantiation used in your example has high risk of producing unintentional coding errors. Named notation is the better way, to my opinion.