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synthesis with design compiler

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cosmonutt

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hi,

have a general question regarding synthesis. i really hope that someone will answer it soon though, my work at school is stuck because of this!!
I have a hierarchical design. there is a top level module. there are some, say four, intermediate level modules M1,M2,M3,M4. and certain small submodules say S1, S2 and S3. to synthesize the design i first created synthesized netlists for the submodules s1,s2,s3. then i synthesized the modues m1, m2 etc.. reading in the already synthesized netlists of s1,s2,s3 into them. s1,s2,s3 are used in more than one intermediate level modules m1, m2 etc. when i finally synthesize the top level module which just joins sub modules m1,m2 etc at the top level, i read in the synthesized netlists for the modules m1,m2,m3 and m4. however, the netlist i get is not unique. in particular, the submodules m1,m2,m3,m4 have unique instances i.e. they seem to have been uniquified. however the lowest level submodules s1,s2 etc are not. when i do uniquify at the top level synthesis i get a warning message that says something like module s1 occurs in module m3 before and, therefore, will be ignored.

what could be the reason for this , and how should i do it in order to get a unique netlist??

thanks![/u]
 

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