muralinmail
Newbie level 1
Hi, everyone,
Is there any proper project organization in Xilinx tool.
Like bringing all HDLs in one folder, EDIF files in separate one, like similar files will be in their respective folder. Separation of Modelsim files, Synthesis files, PAR file etc. I mean 2 say it is just like the structure we can build using FPGAadvantage tool.
If anyone is familiar with xilinx tool can help me, bcz if i open my project folder it is looking uneasy to have all combination of files in one folder.
Thanks,
Murali.
Is there any proper project organization in Xilinx tool.
Like bringing all HDLs in one folder, EDIF files in separate one, like similar files will be in their respective folder. Separation of Modelsim files, Synthesis files, PAR file etc. I mean 2 say it is just like the structure we can build using FPGAadvantage tool.
If anyone is familiar with xilinx tool can help me, bcz if i open my project folder it is looking uneasy to have all combination of files in one folder.
Thanks,
Murali.
