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please send me asic design flow and fpga design flow

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adilkhan123

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asic design flow

please send me asic design flow and fpga design flow
 

Hi,
ASIC Flow:
**broken link removed**
FPGA Flow:
**broken link removed**

Pavlos
 

asic flow: RTL coding-> RTL simulation-> synthesis->dft insert->formal->STA->gate simulation->backend flow
 

ljxpjpjljx said:
asic flow: RTL coding-> RTL simulation-> synthesis->dft insert->formal->STA->gate simulation->backend flow
Click to expand...

It means DFT is before LEC(formal verification)????

What is the meaning of gate simulation???
 

is ASIC design from quartet is the same with that from synopsis

pmat said:
Hi,
ASIC Flow:
**broken link removed**
FPGA Flow:
**broken link removed**

Pavlos
Click to expand...
 

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