assura extraction auLvs

aulvs

Hi guys,

I am currently using Assura320 with EXT712. I have few modules that passed DRC and LVS. I ran RCX from the Assura (which is set to call EXT) and successfully extracted the parasitic components. However as I was running simulations I realized that the netlist generated from the ADE has wrong source/drain diffusion area. Also some of the transistors source and drain connections have been switched.

This lead me to explore the av_extracted view (which consists of auLvs views). And found out that all the extracted transistors had correct width and length, however all of them had the same source/drain diffusion area equivalent to that of a transistor with W/L of 10um/0.35um which is the default pcell startup parameters for the PDK that I am using.

I can manually edit the width of the transistor to a different value and change back to the original to correct the diffusion area however, this method is too tedious for designs with lots of transistors, and also once the av_extracted view is altered, the ADE seems to prevent the user from using the altered av_extracted to generate the netlist to be used for the simulation. Is there something that I should be doing during the LVS process? or during the RCX process? in order to get the source/drain diffusion area correct? Or is this a bug from the PDK?

Thanks for your help,

parasitic extraction issues with cadence qrc

Check the Netlisting options in the LVS window, and try modifyling the order to "schematic auLvs symbol"

Maybe it helps

problems faced while creating qrc decks

it's likely a bug in the PDK from the way you described.

you cannot directly edit the contents in a av_extracted view and netlist it later, it won't work.

if possible, create a very simple testcase and check with the foundry if it's a bug...

how av_extracted views work

Have you verified that the kit you are using support QRC?

how assura checks for qrc?

I have this exact problem. I am able to extract passives with Assura QRC correctly. But transistors has that problem: the source/ drain area are calculated for the default pcell startup W/L parameters for the pdk. hence all parasitics are extracted incorrectly.

I haven't been able to figure out the solution.

generate av_extracted netlist

Let me ask you -
When did you extract - AS/AD ?
-- during LVS extraction stage?
OR
-- during QRC?

The right methodology is - you do AS/AD extraction for all MOS, either during LVS or during QRC.
Remember: You cannot mix this.

If you didn't do it at all during any stage - perhaps defaults values taken its seat - when av_extracted got constructed.

1.
Check the corresponding extractMOS() or extractDevice() statements.

2.
Check the netlist after LVS extraction
cd inside LVS workingdir and run
vldbToSpice lvs_runName.lnn
You can redirect the output to a txt file and check what you see in the extracted parameters of the MOS you are talking about.

3.
If AS/AD is not extracted during LVS, check the QRC/RCX rsf file - you must have **?extractMosDiffusionAp t in rcx rsf

**I am not sure, Cadence might have discontinued the use mode of AS/AD extraction during QRC - so only way left will be to extract during LVS.

Added after 3 minutes:

One more thing -
Typical choice that I have seen across TSMC/CHRT lvs decks, cellview => ivPcell is used more often while creating av_extracted.

Indeed wpchan mentioned it quite right - it might happen CDF callback of the PDK might be having issues.