sivarajm
Member level 1
Hi...
I have to design a one code (VHDL), to operate in 200MHz. I have returned the code. My target tool is Vertex 5. While given the constraints in ISE, i am facing the problem.
3 options are der for clk:
Period:
pad to setup:
clk to pad:
For all the three options I gave 5ns. After place and route, I got
"1 Constraint Failed" as warning. I have attached the message which i am getting.
Can u tell me why it is occurring and how to overcome this problem?
I have to design a one code (VHDL), to operate in 200MHz. I have returned the code. My target tool is Vertex 5. While given the constraints in ISE, i am facing the problem.
3 options are der for clk:
Period:
pad to setup:
clk to pad:
For all the three options I gave 5ns. After place and route, I got
"1 Constraint Failed" as warning. I have attached the message which i am getting.
Can u tell me why it is occurring and how to overcome this problem?