Assura binding issue during LVS !!!!!!!

assura lvs hierarchy

Hi all

I have an issue while running Assura LVS on a mixed signal layout. The layout has DNW devices at every hierarchy. We have a DAC layout which has a logic block placed inside a DNW( so the nch are now placed in DNW in effect but the schematic still states nch instead of nch_dnw).The blocks are LVS clean at corresponding hierarchies but at the top hierarchy, there is a conflict due to the DAC blk. We are unable to give multiple bindings to nch( ie . nch and nch_dnw) as the LVS run aborts.
Assura LVS window gives an option to enable multiple bind_variants.Although this switch is turned on, we get this error.

Any comments as to resolve this issue ASAP are welcome.

Regards
Prathat

assura hierarchy

Hi Prathat,
I'm not too sure if I'm able to understand why there is a bulk potential problem for the DAC digital part. Is the pwell of these nmos devices(in the dnw) connected to the right potential and does it match with the potential you have connected in the schematic?
Does this nch device has a bulk terminal in the symbol? If yes, have you cross checked the connections between the schematic and the layout? I asked you this question because sometimes there will not be a bulk terminal in the symbol and the bulk maybe default connected to "gnd!" or "sub!" in which case there maybe a problem if you have put those devices in the dnw and connected the pwell to some other potential.
One more suggestion is: can you change all the nmos devices in the schematic from "nch" to "nch_dnw" devices?? I think that the nmos model(spectre/hspice) taken for the simulation will be the same regardless of whether the type is nch or nch_dnw..So, it shouldnt change the schematic simulation results at all if you change.
Hope it helps. Sorry if the points are redundant.