Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Negative and floating point numbers in verilog

Status
Not open for further replies.

saima_a

Newbie level 4
Joined
Sep 19, 2008
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,332
Hi all
i want to implement the following mathematical equation in verilog:

slopeup=(y2-y1)/(x2-x1)

slopeup after calculations will be like 0.01456... or -0.013478......... etc.
Plz can anybody tell me how to accomodate numbers like this in verilog???? Plz reply soon. Waiting
 

real types are not synthesizeable, so if you are building any design, 'real' types are hardly of any use.
 

U can use the q-7 numbering format. It is an 8-bit system where msb = -1 and the bits to right are negative powers of 2.

eg : -1 2^-1 2^-2 2^-2............2^-7

u can represent numbers ranging from -1 to 0.99
 

Can it be 12 or 16 bit instead of 8bits???? bcoz values are like 0.0145...etc
 

You can use any fractional number format of your choice, but you should define the application requirements first. Consider, that the division result can be +/- inf as well. Generally, fast (parallel) division is a resource consuming task in FPGA, a serial divider may be a solution.
 

yes u can extend it to any length of vector.
Just increase the negative powers of 2 if u want more accuracy.
 

I tried to search q format on internet but no avail............. what to do for detailed information??
 

im uploading this pdf.. with some info

hope this helps...
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top