$monitor system task in verilog

verilog monitor

Why is $monitor always written inside an initial block?

verilog $monitor

verilog syntax ....

$monitor verilog

Verilog syntax does not say that $monitor will always be inside an initial block. The syntax only says about $monitor.

monitor verilog

Hi ASIC_intl,

$monitor, once invoked, continuously monitors the values of the variables/signals specified in the parameter list and displays all the parameters in the list whenever the value of ANY one of the variables/signals changes.

Since this system task continuously monitors the values, it needs to be invoked only once and hence, it is typically invoked in the initial block since the initial block is also invoked only once during the length of the simulation.

However, it is not necessary that the $monitor statement HAS to be invoked through the initial block. You can invoke it in any procedural block (like always block). In fact, it may be invoked multiple times in conjunction with $monitoron and $monitoroff statements.

Hope this helps.

Regards,
Saurabh

verilog monitor statement

It is used to view outputs in text format on console

$monitor in verilog

We can use $monitor and $display in verilog

This $monitor will display the output when the variables are changing values with respect to time,
$ display is like a printf statement in C language.