Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Neg edge and pos edge DFF in the same clock tree

Status
Not open for further replies.

cafukarfoo

Full Member level 3
Joined
Jul 25, 2007
Messages
170
Helped
8
Reputation
16
Reaction score
5
Trophy points
1,298
Activity points
2,510
Hello Sir/Madam,

I have a clock tree that balance negative edge and positive edge DFF
equally.

Can anyone share what is the pro and cons for this structure?

Thanks.
 

this is usually done when using dual edge FF. the idea is to reduce the frequency by half and operate on both edges of the clock, thus using less power.
(for a short discussion on dual edge FF check here: https://asicdigitaldesign.wordpress.com/2007/07/31/the-double-edge-flip-flop/ )

the price you pay is a much more strict limitation on the clock tree synthesis since you have to account for 50% duty cycle. if you use both edges of the clock you want to have the SAME amount of time on both.

if you are anyways only using one edge of the clock, save the trouble and make your life easier.

ND.

https://asicdigitaldesign.wordpress.com/
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top