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can anyone explain this CMOS comparator circuit to me

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xtingx

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hi
can anyone help me describe this CMOS comparator circuit. this comparator is used for flash ADC. thank very much

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when clk='L', detect the value, and when clk='h', latch the value, why do as this, to increase the speed.

Added after 35 seconds:

it will be call as sense amplifier.
 

In the tracking mode, when CLK is high, M2a and M2b are on. So, the input pair, M1a and M1b is enabled and M0 as a current source will draw current flow from M6a and M6b. while to perform latching mode, CLK is goes low, M2a and M2b are turned off, disabling the input pair. M4 is off, and then output at both M6a and M6b is latched and current from both flows to M5a and M5b.

For example, M6a is high then its output will turn on M5b to connect M6b's output to ground. On the other hand, output of M6b is low so will not turn on M5a and will make the output high of M6a latch there. Out+ and out- is now the result output.

is this explanation correct?
 

I'm not sure this comparator can work well with the the same clk of m2a(m2b) and m4?
 

can anyone explain more detail.... i m very appreciate it , thanks
 

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