analog Design and testing

electronrancher

Hi

I want to to know
how you a designer test his chip
--> logic verification
--> manufactured chip testin

specially interested in analog and mixed signal testing part
I need some good reference in this area too.
|--> book
|--> Professors
|--> site having good reference for starting analog design and its testing related issues

also one more question waht is basic defference in analog design and analog RF IC design (is just that simmulator and model we use for designing is diferent) and what is good platform (simulator) for nalog IC Layout
(is it L-EDIT Cadence ??)

I have asked much any query answer to what ever extend is most welcome
thanks ... sim

problem with lm148

hi,

ur topic is more general. testing as it is is a very big field of research. k, anyhow i would give a general intro to what is taking place in testing.

actually in testing, what becomes difficult is to develop a general algorithm. for example take a synchronous sequential circuit with 100 gates and 100 flip flops. the structure is different when compared to other sequntial circuits and depends wholly on the circuit and the layout of the design.

what at present is being done is generation of so called "Test Vectors". these test vectors are actually those inputs for which u would know the result which u could verify if there is a fault. i would explain a little more on this and wind up.

1) Assume there is a fault somewhere in ur design.(this is a must, i said there are no general fault models).

2) find the input set of combinations(vector), for which u think the fault will be "Propagated".

and this itself is actually no easy as u think. i have given a paper which i think would be useful for u, teesting of asynchronous circuits.

lm148 off

that's digital though.. analog test does not use boundary scan, etc - you would sweep though the threshold of every comparator and watch it trip. Now extract offset, overdrive, etc. Analog test is actually a big field, but a few quick rules of thumb are:
1) Add test mode to allow testing of single blocks, or other options such as turn off oscillator while measuring bandgap to reduce noise.
2) Characterize (or sweep) the threshold of all comparators, inputs, etc.
3) Characterize the output drive strength of any output pins, such as to ensure logic low <0.5v while pin is sinking 1mA - a very common spec.


As for your second question, both Ledit and cadence are good tools. I like Silvaco best, but I work using L-edit at home which is comparable or better in performance. Cadence is actually pretty bad for it's price when compared to either of these guys. Just my opinion, tho! hope this helps - what else do you want to know about test? Give me an example of an IC or datasheet and I'll tell you how to test it.

hi electronrancher,

i think analog testing though is difficult to implement, the whole field of analog is being implemented in only at the chip level. as in the case of discrete ic's say. if we were to tale the case of supecomputers, dsp processors, everywhere digital is there, and also, many many research is goin on in digital testin rather than analog. nevertheless, analog is by itself independent.

regards,
Arun.

Hello electronrancher, waht I am looking for exactly is Analog Opamp design and its test methodologies,
--> which are under reserch
--> which are utilised in industries

there is DSP base technique and signature test, and is utilised in most of ATE (advance test equipments) but I am looking for is possibaly not to involve digital part in testing (like DSP)

also Arun, you re right that most of world being digital and the paper describe is digital asynchronous testing part but are there techniques/resources (kind of I mention in previous mail) are available for analog test techniques then please let me know

other personals are also invited to advice or provide views.

regards...Sim

halo sim,

simphibie said:

Analog Opamp design and its test methodologies,
--> which are under reserch
--> which are utilised in industries

Click to expand...

regarding the book for opamp design, i think the book by author "Sergio Franco" is very very good. though i din't have time to finish the book, i found it interesting. and, by design, what do u mean? a more research oriented book? or is the book i suggest ok. i don't think the book is available either at mcu forum or at elektroda as an e-book. so, u ll have to get it or wait for some time incase u need for that book.


regards,
Arun.

Anything op-amp has been designed and tested to death i think! I'll do a short test list for the LM148, National's version of the 741.

Datasheet is here:
**broken link removed**

A quick look thru the EC table will tell you the test list - TYP is most likely not tested, or just a quick functional test. MIN/MAX are always tested. Any other parameters are guaranteed by the EC table.

1) Input offset voltage - max 5 mV.
-Put 1v on (+) terminal and loop output back to (-). Read ouptut voltage. should be .995 to 1.005v

2) Input offset current - max 25nA. Usually similar to #1, except now you put 10k or 100k in series with each input. If offset voltage is already known, measuring voltage drop across each resistor will give you Ios. (Difference between drop/R)

3) Input bias current - max 100nA. Average of the two currents measured in #2. Reuse measurements for both of these tests saves test time.

4) Input Resistance - min 0.8 MEG. Check Input bias current at 1V and 5V, Difference is bias currents gives Rin

5) Supply current. Set (+) to midrange (0v), loop Vout to (-) again. Measure Icc..

6) Large signal voltage gain. min 25V/mV. Says VOUT=+/-10v, so probably 10k/1k resistor divider in standard inverting configuration. Set Vin=1v, 0.995, and 1.005, and check for 10, 9.95 and 10.05, etc.

7) Amp-to-amp coupling. - TYP only, user gets no guarantee! A good test engineer will have swept the parts with AC 1kHz to 20kHz, found the worst point, and put a quick sanity check in their test to screen out gross defects. (But designers HATE yield loss due to typ, so they may make you take it out if it's a problem)

A bunch more TYP's, then a few more easy tests and you're done! I would estimate 300-500mS test time for each channel, so maybe 1-2seconds overall.. Hmm that seems too long for a 741 maybe.. I was testing dual DC-DC in 1 second at my old job - they contain about 10 amps, oscillator, logic, current limit, etc..

As an example of some source code for the test program, let's assume I have a set of relays that either loops back input-output clean, or with 100k on each input.
//--------------------------------------------------------
//Vos test
//--------------------------------------------------------
myrelay->open_relay(); // loop back clean signal
delay(3);// 3ms relay settle time
Vneg->set_voltage(1.0, RANGE_2_VOLTS);
delay(1); // 1ms voltage settle time
mynegative=measure_voltage(Vneg);//Get V(-)
mypositive=measure_voltage(Vpos);//Get V(+)
myoffset=mynegative-mypositive;
datalog(myoffset);


And so on...

hello electronrancher,

i got the paper but I am at present looking for CMOS base design of OpAmp, my aim is to test opamp with in mixsignal IC.
I want to design first an opamp and simulate using it Hspice.

can some one provide me specification of OPAMP required to built an opamp using NMOS and PMOS transisters. like
CMR
CMRR
slew rate
input offset voltage/current allowed
other ...
also the steps one has to follow to transform this specs into w,l of transisters.

thanks
Sim

hehe can anyone do my project for me?

cmrr is output impedance of your mirrors, slew rate is current thru the branches of your diff pair into or out of your compensation cap. vos is matching, ios only needed if you use bipolar. and last but not least, gain is gm of diff transistor * rout of diff pair in parallel with rout of diff mirror.

simphibie said:

hello electronrancher,

i got the paper but I am at present looking for CMOS base design of OpAmp, my aim is to test opamp with in mixsignal IC.
I want to design first an opamp and simulate using it Hspice.

can some one provide me specification of OPAMP required to built an opamp using NMOS and PMOS transisters. like
CMR
CMRR
slew rate
input offset voltage/current allowed
other ...
also the steps one has to follow to transform this specs into w,l of transisters.

thanks
Sim

Click to expand...

The most important parameter in Op-Amp are:
Voltage oFset
Bias current
Gain
PSRR
CMRR
Lo ok at these definition on any bo ok about Op-amp.
you also learn how to test it too

just read book analysis and design of analog integrated circuits or analog cmos design