What is the "Total cell area" unit in synopsys rep

total cell area

Hello all,
I synthesized a single NAND gate to find out the gate count relation with the Total cell area for two technologies lsi_10k and umc180. The result is for Lsi-10k the "Total cell area = 1.000" and for umc180 the "Total cell area = 12.19700" with out a unit.

In the library of these technologies the time unit is clearly specified in nano seconds (ns).

But, I can not find the unit of the area in the library umcl18c250t2.db and lsi_10k.db. How do i know the unit? Is it in sqare nanometer (sq. nm) or micro (sq. um)?

Thanks,
mogogo

synopsys total cell area

It's probably different for different libraries. You won't get much correlation data until you do an initial place and route probably.
I'm guessing for the LSI lib, the total cell area is counted with respect to a single two input NAND gate, which is why your result is 1. TSMC does something similar.
For the UMC lib, I don't know. Square microns would be a reasonable guess too. square nm is too small for one NAND gate in .180 micron technology.
You need to look at the library's datasheet to be sure.

how to calculate cell area um^2

gliss said:

It's probably different for different libraries. You won't get much correlation data until you do an initial place and route probably.
I'm guessing for the LSI lib, the total cell area is counted with respect to a single two input NAND gate, which is why your result is 1. TSMC does something similar.
For the UMC lib, I don't know. Square microns would be a reasonable guess too. square nm is too small for one NAND gate in .180 micron technology.
You need to look at the library's datasheet to be sure.

Click to expand...

Thanks gliss,

if we assume it is sq. um, then one NAND gate is 1sq.um in LSI_10k and 12.197sq.um in UMC180. But still, why would this gate size be bigger in UMC while we know that gate size shrinks for every technology?

nand cell area synopsys

No, I don't think that the gate size for that 1 NAND gate in LSI 10K is 1 um^2.
When they say the gate size is 1, they mean the gate size is equivalent to 1 NAND gate, which should be obvious since your design only has 1 NAND gate. In fact, the term "gate count" would be more accurate. Since the units really are just gates.
TSMC does something similar, one 2-input NAND gate is 1, 1 2-input AND gate is 1.5, an inverter is .5, a 2-input NOR is 1, a 3-input NAND is 1.5, a 4-input AND is 2.5, a 1-bit half adder is 4.5 and a D flip-flop is 6.5. But in the TSMC datasheet, it also says that the width of 1 NAND gate is 0.5600um (45nm technology). So I can calculate width of any cell because I have the width of one NAND gate and the sizes of all the other cells expressed in NAND gates.
This is why I said to look at the library's datasheet.