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Logic synthesis, regarding area

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E

engr

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Hi All,

If i see the area report after compiling the design, report showing the , area information about each cell and each sub design and area of combo logic and area of seq logic.

I didnt understand, what this area means, is it the physical area ? i cant able to visualize what this area means.
pls give me more elaborative explantion

Thanks in advance
 

Yest it is the physical area represented in terms of library units. Each cell in library has its area defined in .db file. Synopsys dc adds up the area consumed by each cell to give total combi and sequential area in its report.
Hope it helps
Kr,
Avi
 

    E

    engr

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Thanks avimit,

It means, that much area taking at final layout ?
 

engr said:
It means, that much area taking at final layout ?
Click to expand...
Area after layout will be bigger, due to the P&R tool not being able to utilise 100% of die area. E.g. typically utilisation will only be 80%.
 

    E

    engr

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IN the library each cell has an area of value 6.0, 4.4 etc .What are these values? What do these values signify?
 

ASIC_intl said:
IN the library each cell has an area of value 6.0, 4.4 etc .What are these values? What do these values signify?
Click to expand...
Area in um^2, probably.
 

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