high speed cmos pll(7GHz) in 0.13 cmos tsmc, delay vco

hi all,

i need a little guidence. i am trying to design a high speed cmos pll(7GHz) in 0.13 cmos tsmc. I want to use a 4 delay cell Vco.

I would like to ask any of u if i can get Kvco around 3GHz/v.
it looks that because of the low power supply(1.2V) i will have a pretty small control zone which will give me the Kvco mentioned before.

the second question is about the current-controlled delayc ell vs. voltage controlled one. i have a feeling that the current is easier to control and design. do u have any input?

thx. cretu

pll high speed

I am not quite sure about your first question of 3GHz/v. I think however that you can probably do it and it is in a way linked to your second question. To me the current controlled cell is preferable and easier to control. More to this you'll be able to at least assure some kind of high impedance to supply through your controlled current source which in turn will be beneficial for your jitter figures. Because you're controlling the frequency by controlling the bias current of the cell may be you'll be able to get bigger Kvco than if you would control somewhere some voltage. That's my feeling.

high speed pll

In real case

Uxx 0.25um PLL max freq --> 1G (some worst case limit to 1GHz)
0.18um PLL --> 2GHz is OK

why use 7HGz PLL on your design ?? high speed design usuall use
"clock data recovery " --> multi_phase clcok signal ..

like serial_ATA 1.5Ghz , but you can not use 15GHz PLL for lock it
maybe circuit can do it , but it is bad idea ..
we use multi_phase 1.5Ghz sample it (clock data recovery)..

Re: High speed PLL design

Cretu,

I probably can't help you much with your problem, but if you could clarify something for me I would appreciate it.

How do you create a VCO with 4 delay cells? Years ago (0.8u days) when I did some VCO work I used simple inverters to create a ring oscillator. If I remember correctly, the p-channel devices had their gates tied high, and the control circuit was connected to the gates of all the n-channel devices. However, in order for the ring to oscillate, you needed an odd number of inverters. How do you get your ring to oscillate with an even number of devices?

It's probably something obvious but as I mentioned I haven't done this kind of work in years.

Thanks,
Radix

Re: High speed PLL design

hi radix

the oscillation condition doesn't necessarely require an odd number of inverters/delay cells. with a 4 (or any even number) you can get quadrature outputs for the clock. By using 4 cells my plan is to get 8 phases for one given frequency

Re: High speed PLL design

andy2000a said:

In real case

Uxx 0.25um PLL max freq --> 1G (some worst case limit to 1GHz)
0.18um PLL --> 2GHz is OK

why use 7HGz PLL on your design ?? high speed design usuall use
"clock data recovery " --> multi_phase clcok signal ..

like serial_ATA 1.5Ghz , but you can not use 15GHz PLL for lock it
maybe circuit can do it , but it is bad idea ..
we use multi_phase 1.5Ghz sample it (clock data recovery)..

Click to expand...

hi andy2000a

i need the 7 GHz because i have 14GB/s data coming in and i am using both edges of the clock to sample the data. I also need some high speed correction for the data stream. As for Serial ATA 150(or 1.5 GB/s) i have worked on a chip that's doing exactly that. We were using for both transmit PLL and CDR 750MHz PLL's

Re: High speed PLL design

Radix,
This ring oscillator that you remember is just one approach, not necessarily the best. You can make a ring oscillator with 4 cells (or any even number of cells) if you use a differential structure. In all ring oscillators you need invertion around the loop to get oscillation. In single ended design you have to have odd number of inverters. If you use differental cells, however you can do inversion simply by crossing the outputs - if outA, outB is the straignt, then obviously outB,outA will be the inverted. This way you can make a ring oscillator with even number of cells.

If u hook up with 4-cell differential ring oscillator running at x MHz/GHz, equivalently u will get 8x MHz/GHz clock if u can make use of all the outputs of every single stage of ring osc.

Re: High speed PLL design

sutapanaki,

Thanks for the clarification. I was at a loss as to how a series of non-inverting delay cells could oscillate.

radix

Re: High speed PLL design

Why dont you choose LC tank VCO? Most VCO published in JSSCC whose work range is beyond 3GHz are implemented with LC tanks.

Re: High speed PLL design

If you use VCO gain of 3GHz/V, you must suffer pure phase noise and large spur level!

Re: High speed PLL design

if u use LC tank VCO , there is some work that get about 5GHz using .25 cmos technolgy , so u can use .18 or .13 to get much higher
about the quality factor of inductor u can get higher quality factor in .13 and .18 , because the metalization is CU , insted of Al , so the serise resistance will be less

about the high KVCO , i think donot worry about it , because the control voltage is the voltage around the loop filter , i think it doesnot depend on the VDD , but it depends on the charge pump current

Re: High speed PLL design

nativeda said:

Why dont you choose LC tank VCO? Most VCO published in JSSCC whose work range is beyond 3GHz are implemented with LC tanks.

Click to expand...

the technology it's more expensive to begin with but you can get really good VCO's up to 5-7GHZ with a ring oscillator.It's easier if u can't get good Q for the inductors

cretu

Re: High speed PLL design

I think that it would be very tough to obtained such a high voltage sensitivity through ring oscillator. And Even if some how you are able to get one the sensitivity of your VCO to various common mode variation such as supply variation and substrated coupling will be very high. and since at such a high frequency your budget for the allowable jitter is very tight and you cannot afford to loose any further.
What better will be to use the charge pump operating at higher voltage (device with thicker gate okide) and reducing the sensitvity of the VCO.
Other option will be to use the LC Tank oscillator (It will have better phase noise then the ring oscillator one.). But the disadvantage will be that tuning range will be lower then that in case of ring oscillator which you can take care of by using the switch cap type of oscillator where you can have both coarse tuning and fine tuning.
othere option will be to use All digital pll.

What you feel.

Amit