Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

PLL IN STRATIX II or STRATIX III

Status
Not open for further replies.
K

kumarshravan1

Newbie level 1
Joined
Feb 7, 2006
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,286
stratix iii pll

How can I get a clock frequency of 528MHZ, 330MHz and 66Mhz from a single PLL and which device is supporting it. What should be the input frequency and what are the ratios that needs to be set for obtaining those results
 

Consider a VCO operation range of 600 to 1300 MHz for Stratix III and integer pre and post dividers, and you'll see, that it isn't possiblewith a single PLL, although the three frequencies have integer ratios. It's possible with two cascaded or independant PLLs only, I think.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top