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Reset buffering for digital block with asynchronous reset

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lhsj81

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Hi All,

When designing a digital block with asynchronous reset, should this reset be buffered?
Some of the standard templates (for sdc) seems to have the reset port as an ideal_driver and path disabled. If this is the case, wouldn't the reset pin be overloaded?

Currently I have set the external_driver and load constraints on the asynch reset pin of my module, however I was wondering whether such an approach is the preferred method, (I am still quite new to the digital synthesis and was hoping to follow the standard procedures).

Thanks,
Regards,
Louis
 

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