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a question about DDR memory

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kequal

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We've developed a DDR memory controller in Xilinx FPGA. The waveform of the control signals from FPGA to DDR memory seem to accord with the specification well, but the datas read from the memory ofen do not equal to the ones been written to it.
Did anybody has any experiences about such situation?
BTW, the voltage of the DDR memory is not quite good. It has a +/-100mv shift. Is this the reason for that?
 

What do you mean by often?

This behaviour normally suggest either a problem in your Voltage as you suggested or more importantly a problem in your timing?
Try to capture in your scope or Logic Analyser or wherever a single access when is not reading back properly?

Bear in mind that the problem could be in the read cycle
or in your write cycles 8)

I would also suggest you to change the pattern man, all ones :D
Use AA55AA55 os something like that.

What FPGA are u using? What DDR memory?

-maestor
 

Thank u very much!
By often I mean sometimes the datas read back are right, but in most cases are wrong.

We've used scope to capture the waveforms of the signals and they accord with the timing specification quite well.

We've tried several address patterns and the problem still exits.
 

Looks like it might be a timing issue like maestor says.
If it is very important to understand whar kind of DDR memory you are using. If it is DDR SDRAM, what is the frequency of operation? and what is the propogation delay between your memory and the FPGA?
 

Hi kequal,

first I would try speeding down the whole access as much as possible. I only know SDRAM not DDR RAM but they should work similar. I know that SDRAMs can work at different CL-timings, so try to increase it to be sure you are not accessing too fast.

Do you update the DDR RAM State Machine to your timing parameters?? Is it possible to read back the DDR RAM's statemachines adjustments??

If your data timing is according to the specifications your DDR Ram must be programmed to exactly the same timing and access type you are doing. otherwise you will have a missunderstanding.

Is there an example Code for DDR Ram implementation for your FPGA you can look at??

-aOxOmOx
 

I designed a SDRAM controller long time ago. My suggestion is:

1. Check the 'refresh' period. The contents of SDRAM should be refreshed within certain period according to spec, either by auto refresh or manual refresh. Otherwise what you write in will be lost. To verify wheter it is this problem, you can do a read immediately following the write at the same address.
2. Check the rising edge of clock. It should be clean.

regards
 

Hi,
Try capturing the data bus of DDR for write cycle and read cycle
in an Logic Analyser. U can isolate whether the problem is with read or write.
-kib
 

Are you simulating your design? I design an interface to a ZBT SRAM last year and I got the behavioural model from the supplier I added it to my testbench and run a post place and route simulation. The write cycle worked first time bet there were a couple of issues in the read cycle, easy to fix if the model is accurate and your testbench is not bad :p

So maybe is worth you doing a post PAR simulation.

-maestor
 

Hi,

The power supplying of DDR:s is critical!
Do you manage to maintain the noise level on Vref within +- 25 mV?
Are you using e.g. an ML6554 regulator to supply the DDR?

DDR:s are analogue components... ;)

/Ram
 

I think you should check the delay from I/O pin to DFF in FPGA. Maybe they are critical !!
 

Hi kequal,

Are you getting the read data properly now? I'm also into DDR SDRAM controller design and i'm facing the same problem like yours. I have also taken care of all the solutions posted by our friends.
Please revert back with your suggestions.

Thanks in advance.

Regards,
kams
 

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