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Constraint for input pin in synthesis

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cafukarfoo

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Hello everyone,

I need your advice here.

I have a input pin which is a data pin. But some of logic depend on the
rising/falling of this input pin.

For example,
module test ( A, B, C, D, clk);
input A;
input C;
output B;
output D;
input clk;

always @(posedge A) begin
B <= C;
end

always @(posedge clk) begin
D <= A;
end

In this example, flop B created with the clk pin attached to the A pin.

So in the constraint file, how should i constraint A?

Thanks in advance for your help.
 

1. You are using A as a clock. are you sure you want to do that?
2. Since A is also a clock, you have muliple clocks.

Now you can constrain A, with respect to the clock clk. and you can constrain C with respect to the clock A.
You will also have to false path between clcok A domain and clock clk domain.
Kr,
Avi
 

Hi,

In the example you have given both signal A and signal clk are supposed to be defined as clocks in synthesis. Since you A is a data pin find out whether you need to do any timing analysis on the paths that are in this clock domain. Depending on which you either declare the paths clocked by A as false paths or as a different clock domain.

Thanks
Prasad.
cafukarfoo said:
Hello everyone,

I need your advice here.

I have a input pin which is a data pin. But some of logic depend on the
rising/falling of this input pin.

For example,
module test ( A, B, C, D, clk);
input A;
input C;
output B;
output D;
input clk;

always @(posedge A) begin
B <= C;
end

always @(posedge clk) begin
D <= A;
end

In this example, flop B created with the clk pin attached to the A pin.

So in the constraint file, how should i constraint A?

Thanks in advance for your help.
Click to expand...
 

Hi Avimit and anssprasad,

Actually a lot of internal logic in my design will use the data A.
And main clock for my design is clk.

So if i define A as a clock, i feel something is wrong with this.

A lot of clock gating for A will complaint by the DC.

I am thinking a better way to handle this situation. Either change the
RTL or define the A pin in a better way
 

Hi ljxpjpjljx,

If in this case, i insist to maintain the RTL, what is the best way to
constraint the pin A for synthesis run?

Thanks.
 

If there is any signal that is going to the clock input of a flip flop then there is no other way out but to define it as a clock in DC. If you find any please let me know.
 

Hi anssprasad,

In my case, there is only 1 flop drive by the pin A. Others flop drive by clk pin.

So i use the "set_max_delay" and "set_min_delay" for the flop drive by pin A
to constraint it for setup and hold time check.

If you got better opinion, please let me know. thanks.
 

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