voho
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HI ALL,
How to do for SSTL2 Class II in order Interfacing Micron DDR Memories to Xilinx virtex4.
Specific Guidelines for Virtex-4 FPGA I/O Supported Standards UG070
Whe need resistor only for data bus and/or bus adress in not clear?
thank's in advance
best regards
How to do for SSTL2 Class II in order Interfacing Micron DDR Memories to Xilinx virtex4.
Specific Guidelines for Virtex-4 FPGA I/O Supported Standards UG070
Whe need resistor only for data bus and/or bus adress in not clear?
thank's in advance
best regards