Reasoning behind active low signals

Hi All,

I am a new bee into VLSI field. I was going through some of the coding guidelines for the HDL and one of them stated "The signals are to be designed ative low preferably."
I tried searching in the internet for the reasoning behind , foun some which was not convincing at all . They say and i quote
"If you consider the transistor level of a module, active low means the capacitor in the output terminal gets charged or discharged based on low to high and high to low transition respectively. when it goes from high to low it depends on the pull down resistor that pulls it down and it is relatively easy for the output capacitance to discharge rather than charging. hence people prefer using active low signals"

Can any one please let me know what exactly the reasoning behind making the signals active low

Thanks in advance
Abhiiii

hi abhi

i dont know how correct i may sound but Active low simply states that the certain logic or circuit becomes Active or enabled when u apply a low signal to it ,
Using Active low signal can have the advantage of low power dissipation

i also suggest u to go through some reading material related to GROUND BOUNCE
u may find some significant answers to ur questions

Anybody correct me if i am wrong

I don't see a plausible reason for active low signals with today's CMOS logic. It's partly convention and partly TTL legacy. With TTL I/O, high level is the lower current idle state. Assuming symmetric CMOS logic thresholds, interference susceptibility isn't different for high or low idle level.