vhdl code for pulse generator

Hi guys
I want vhdl code for generating a pulse
of following specifications
PW=1us, 1ms
for PW=1us, 1us=Ton and 1us=Toff
Means it is 50% duty cycle.
I have implemented this code


entity pulse is
Port ( clk : in std_logic;
res : in std_logic;
clk_div : out std_logic);
end pulse;


architecture Behavioral of pulse is
signal count : integer;
signal temp : std_logic;

begin
process(clk,res)
begin
if res='1' then

temp <='0';
count <= 0;

elsif (clk'event and clk='1') then
if (count = 38) then
temp <= not temp;
count <=0;
else
count <= count +1;

end if;
end if;
end process;
clk_div <= temp;

end Behavioral;

But Im not getting proper PW=1us I m using 40 MHz Clock. I have simulted in Model sim
Plz Let me favour

Yes, you programmed 40/39 = 1.025 us. And don't forget to disable the smilies when passing code as html text.