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Simulation with VHDL: How to create stimulus with Jitter?

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Black Jack

Black Jack

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Hello!
I`m need to create clock stimulus with jitter.
I think that need to generate random numbers in desired range and
add/substract from constant for period.
What you think about this?
Can anyone share examples of VHDL code?

-- Regards, Jack
 

Re: Simulation with VHDL: How to create stimulus with Jitter

You are on right track! That the way we generate clock with gitter!
 

You must use functions in "ieee.math_real" library to generate random numbers in a limited interval.
 

Re: Simulation with VHDL: How to create stimulus with Jitter

tohidsedghi said:
it is perfect
Click to expand...

1) Whats "perfect"? :)
2) Thanks for gurus from https://verificationguild.com.
They advise me with code like this

Code: 
sys_clk_process:  process
    -- variables for uniform
     variable seed1, seed2 : positive;
     variable r : real;
  begin
    uniform(seed1, seed2, r);
    d <= r * 1 ns;
    wait for SYS_CLK_PERIOD/2;
    clock <= '0';
    wait for SYS_CLK_PERIOD/2;
    clock <= '1'; 
end process;

sys_clk <= transport clock after d;
 

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