Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Warnings in The log file.

Status
Not open for further replies.

suresh etikala

Newbie level 3
Joined
Jun 28, 2008
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,296
Hi E'one,

How can I supress/disable compilation warning messages in the logfile.
I am using cadence nc-verilog simulator.

Thanks in advance.

bye.
 

when you run simulation , you can add "nowarn" option to select which warning you want to supress!
 

I am sorry, I could not get you..
Could you explain me indetail..

Thanks in advance..
 

ncverilog have a option to suppress some types of warning message. Just as, ncverilog +nowarn+<arg>
This option is used to disble printing of the specified warning mesage.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top