atif.india
Newbie level 3
Hi,
I am writing a code for Ethernet assemble where i have to first read the first loc of memory (32 bit) place the data in 8 bit temp loc (changing after every two clock cycles) then increment the mem pointer and do the same( this time it's only the fist 16 bits). I have used mod counter for the purpose. My prog looks like this
module assembler (data,strt,eof,err2,clk,rst,buf_data,buf_addr);
output reg [7:0] data;
input strt,clk,rst;
output reg eof,err2;
input [31:0] buf_data;
output reg [8:0] buf_addr;
reg [31:0] frame;
always@(buf_data)
frame=buf_data;
reg [3:0] mod8=4'd0;
reg [2:0] mod4=3'd0;
parameter idle=3'd0;
parameter desadd=3'd1;
parameter desadd2=3'd2;
parameter sadd=3'd3;
reg [2:0] state;
always@(posedge clk)
begin
if (rst)
state=idle;
else
case (state)
idle: if (strt)
state=desadd;
else
state=idle;
desadd:
if (mod8==4'd8 )
state=desadd2;
else
begin
state=desadd;
mod8=mod8+4'd1;
end
desadd2:
if (mod4==3'd4)
state=sadd;
else
begin
state=desadd2;
mod4=mod4+3'd1;
end
endcase
end
always@(state or mod8 or mod4 or frame)
begin
case(state)
idle:
begin
data=8'd0;
eof=1'd0;
err2=1'd0;
buf_addr=9'd0;
end
desadd:
begin
case (mod8)
4'd0: data=frame [31:24];
4'd1: data=frame [31:24];
4'd2: data=frame [23:16];
4'd3: data=frame [23:16];
4'd4: data=frame [15:8];
4'd5: data=frame [15:8];
4'd6: data=frame [7:0];
4'd7: data=frame [7:0];
default: data=8'd0;
endcase
end
desadd2:
begin
buf_addr=9'd1;
case(mod4)
3'd0: data=frame [31:24];
3'd1: data=frame [31:24];
3'd2: data=frame [23:16];
3'd3: data=frame [23:16];
default: data=8'd0;
endcase
end
endcase
end
endmodule
When i comment out the state desadd2 and use only desadd i am getting proper output (data is taken in from buffer and is changed every two clk cycles) but the moment i add the next state my op completely disappears. What could be the prob with this case. One warning that i am getting is there is prob with inferring latches which holds its perv value in one or more path trhu always construct .
I am writing a code for Ethernet assemble where i have to first read the first loc of memory (32 bit) place the data in 8 bit temp loc (changing after every two clock cycles) then increment the mem pointer and do the same( this time it's only the fist 16 bits). I have used mod counter for the purpose. My prog looks like this
module assembler (data,strt,eof,err2,clk,rst,buf_data,buf_addr);
output reg [7:0] data;
input strt,clk,rst;
output reg eof,err2;
input [31:0] buf_data;
output reg [8:0] buf_addr;
reg [31:0] frame;
always@(buf_data)
frame=buf_data;
reg [3:0] mod8=4'd0;
reg [2:0] mod4=3'd0;
parameter idle=3'd0;
parameter desadd=3'd1;
parameter desadd2=3'd2;
parameter sadd=3'd3;
reg [2:0] state;
always@(posedge clk)
begin
if (rst)
state=idle;
else
case (state)
idle: if (strt)
state=desadd;
else
state=idle;
desadd:
if (mod8==4'd8 )
state=desadd2;
else
begin
state=desadd;
mod8=mod8+4'd1;
end
desadd2:
if (mod4==3'd4)
state=sadd;
else
begin
state=desadd2;
mod4=mod4+3'd1;
end
endcase
end
always@(state or mod8 or mod4 or frame)
begin
case(state)
idle:
begin
data=8'd0;
eof=1'd0;
err2=1'd0;
buf_addr=9'd0;
end
desadd:
begin
case (mod8)
4'd0: data=frame [31:24];
4'd1: data=frame [31:24];
4'd2: data=frame [23:16];
4'd3: data=frame [23:16];
4'd4: data=frame [15:8];
4'd5: data=frame [15:8];
4'd6: data=frame [7:0];
4'd7: data=frame [7:0];
default: data=8'd0;
endcase
end
desadd2:
begin
buf_addr=9'd1;
case(mod4)
3'd0: data=frame [31:24];
3'd1: data=frame [31:24];
3'd2: data=frame [23:16];
3'd3: data=frame [23:16];
default: data=8'd0;
endcase
end
endcase
end
endmodule
When i comment out the state desadd2 and use only desadd i am getting proper output (data is taken in from buffer and is changed every two clk cycles) but the moment i add the next state my op completely disappears. What could be the prob with this case. One warning that i am getting is there is prob with inferring latches which holds its perv value in one or more path trhu always construct .