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Problem with connecting Virtex-E FPGA to JTAG

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EDA_hg81

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I am debugging a virtex-E FPGA, its original configuration setting of M0, M1 and M2 are 011 ( SelectMap).
I have changed the setting of M0, M1 and M2 to 101 for JATG configuration.
I can connect the FPGA with JTAG, but program didn’t work.
What is the problem?
The same program is used for SelectMap configuration and JATG configuration.
Thanks.
 

JATG does not work

Which program didn't work? iMPACT? Did it give you any error messages?

Or are you saying that SelectMap works but JTAG doesn't? What are the symptoms? Error messages from iMPACT? FPGA behaves strangely?

By the way, the bitstream that we download into an FPGA is called a "configuration" or sometimes a "design". We don't call it a "program".
The acronym is spelled JTAG. It means "Joint Test Action Group".
 

    E

    EDA_hg81

    Points: 2
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Re: JTAG does not work

both Selectmap and JTAG download are successful.
In my testing, the Input Clock was rerouted out for testing.
But the output should reflect input clock is not toggled.
I think there are two reasons for this:
1. Component instantiation is wrong.
2. Something is wrong with configuration mode setting.
I am sure the Component instantiation is right.
So I think there something else is wrong.
Thanks.

Added after 1 hours 20 minutes:

Just found out all the pin locations are messed up.

I am using ISE foundation 9.2I.

How this can happen?

such as my GCLK should be at B8, but the result is R8.

what is wrong?
 

JTAG does not work

ISE provides several methods for you to specify desired pin locations. Which method are you using?

Be sure you have selected the correct FPGA type and package type in your ISE project.

Maybe a simple syntax error occurred when you specified "B8", so ISE used a default pin instead.
Try searching for warning messages that mention "B8" or "R8". You may need to search through ISE's log files.
 

    E

    EDA_hg81

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Re: JTAG does not work

ISE don't generate any warning messages .

I check the foorprint on FGPA surface. I think I am using the right Package.

For assigning Pins I am using Xilinx Pace.

I also check pins assignment at Assign package Pins Post_Translate.

until above steps, the pins assignment are all right.

But the pin assignment is wrong at Map.

I am trying using manually Place and Route ( FPGA editor) to fix it.

Do you have any suggestions about using manually Place and Route ( FPGA editor)? Since I never use manually Place and Route ( FPGA editor).

Hope I am lucky enough.
 

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