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sending data to a hardware acclerator

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snake0204

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Hi Guys,

I need a little advice here with Xilinx XUP board. I developed a HW accelerator for a video processing task. I write pixel data along with some additional data word by word to HW accelerator through software, but this writing data through software is slowing the system down, in the sense I am getting very low frame rate.

Unfortunately there is not enough BRAM space on the FPGA to store the whole frame and the additional data, so I have to store all this data on SDRAM and write it to HW bock pixel by pixel and then frame by frame.

I am using a Xilinx XUP board with linux running on the PPC. One ideal solution would be to have a DMA and write a device driver but I don't have resources and expertise in this area....is there any easy way around this bottle neck.

Thanks
Ramc
 

What is your hardware architecture? I mean did you include a DMA controller in your design, which comes with driver support. DMA is probably the best/fastest way to get large amounts of data into your accelerator
 

Thanks for the response, my hw acc does not include any DMA. The block is interfaced to a OCP bus (to enable design reuse we use OCP bus interface for all our blocks). So in effect there is a PLB-OCP bridge and all the hw acc sit on this OCP bus. So what we need is probably a DMA sitting on the PLB bus that can access SDRAM.

It is very interesting to know that there is a DMA with driver support, can you please throw some light on that. Thanks
 

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