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Problem with LPC Bus interface as the LFRAME# signal is always high

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Zhane

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Im trying to make a LPC bus interface to record the bus traffic as a result of keypresses.

Im using the clk from the LPC bus as my process clock. But it seems that the LFRAME# signal is always high and never drop low.

Im using the I/Os on the spartan 3e fpga to do the probing.

Anyone has any idea what I can do?
 

interfacing fpga to lpc

please provide the timing diagrams of the bus transactions i.e. read and write cycle of the bus.
 

lpc bus fpga

The clock of this bus is running at 33Mhz.

I'm wondering if Im using the right I/O with the right setting to probe it

I'm using LVTTL, default drive and default slew to probe
 

Re: LPC Bus Interface

you can verify the signals in DSO. Sampling other signals on the LPC clock rising edge should not miss any state.

If you want to incorporate the peripheral on LPC, then you have to implement the MAC layer in FPGA. It requires in depth inderstanding of the protocol.
 

Re: LPC Bus Interface

erm what is DSO?

I sample it on the rising edge of the LPC bus, but Im not sure what's wrong but the output values doesnt seem to be the right stuffs
 

Re: LPC Bus Interface

DSO = digital storage oscilloscope,
alias the good old CRO (= cathode ray oscilloscope)

:|
 

Re: LPC Bus Interface

dont have that kind of luxury ;(
 

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