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Max cap & tran limit in SDC

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fail1

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we need to set the fanout & tran limit in our SDC file.
In 130nm designs, we were setting the fanout & tran as "1"
But need to come up with these numbers for 65nm designs.
What is the general procedure for coming up for this number?What do people normllay set max cap & max tran limit in their sdc files for 65 nm designs.
 

you can check your 65nm standard cell library for reference!
 

Thanks!
so, whatever is set in our library, thats the number we should use for optimisation..?

Meena
 

yes, for normal case, library setting can meet your request such as fanout&tran. but for some special case you need to set your own constraints (more strict than the library setting) such as clock tree path.
 

fanout to 1 ?
I think the tool will choke.

use 10-20 for fanout, use 10% clock for tran.
 

No, I meant fanout as 70 & tran & cap as "1"
 

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