Zhane
Member level 5
Hi... sorry to bother you guys again
I've just recently generated a FIFO core with Xilinx's Coregen... to use with my uart
according to my Modelsim simulation, it seems that no data is being written into the FIFO, even after doing wr_en <='1'
is there any examples out there that I can use as a reference?
i know that there's a uart core at opencores, but its been a while and they have not approved my account creation yet.
I've just recently generated a FIFO core with Xilinx's Coregen... to use with my uart
according to my Modelsim simulation, it seems that no data is being written into the FIFO, even after doing wr_en <='1'
is there any examples out there that I can use as a reference?
i know that there's a uart core at opencores, but its been a while and they have not approved my account creation yet.