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How to use Xilinx coregen FIFOs?

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Zhane

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Hi... sorry to bother you guys again

I've just recently generated a FIFO core with Xilinx's Coregen... to use with my uart

according to my Modelsim simulation, it seems that no data is being written into the FIFO, even after doing wr_en <='1'

is there any examples out there that I can use as a reference?

i know that there's a uart core at opencores, but its been a while and they have not approved my account creation yet.
 

xilinx coregen fifo

Its very simple to use Xilinx coregen FIFOs. Just make sure that you have applied proper clock to the FIFO and it should be up all the time. Then follow the steps below:
1. Make sure data to be written is available and stable.
2. Put it on "din" signal. Don't assert "wr_en" at the same clock edge when you put data on "din".
3. After a while, assert "wr_en" for a single clock cycle. Before executing this step, dont change the data. It may cause you to put wrong(garbage) data into the FIFO.
4. After a while, update data on "din" or goto step 2.

Now you should get the data into the FIFO.
 

xilinx+fifo

hmm

how to make sure my data is stable first? and how to do wr_en at another clock?

sorry i'm really really very noob at this.

Am I doing it in code below?
 

fifo with xilinx cpld

Complete your state machine buddy! I am not sure what are you trying to implement? Following state descriptions may help you:

1. IDLE state: wait in this state until you get the new data, after having data goto 2.
2. Start WRITE state: Assert wr_en, goto 3.
3. Stop WRITE State: Deassert wr_en, goto 1.
 

data fifo xilinx

managed to get something that looks right on my simulation


but i'm having problem simulating my uart... the supposed output of my fifo
i can see the fifo data coming out..but my uart is dead =(
 

coregen fifo simulation

Hi,

UART code is attached for your reference.
 

simulating a xilinx fifo

thanks for ur code
but i dont understand verilog =(
 

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