deepu_s_s
Full Member level 5
illegal reference to net verilog
Hello friends,
I am facing some problem with the code. I am implementing a algorithm in verilog. The code below i pasted is a butterfly code.
The inputs to the butterfly are 4 words each of 12bits..
The outputs to the butterfly are 4 words each of 14 bits.
`include "adder.v"
module butterfly(row , result);
input [9:0]row[3:0];
output[10:0]result[3:0];
wire [10:0]t[3:0];
wire [11:0]temp_result[3:0];
wire [11:0]temp_input[1:0];
wire [3:0] size;
assign size = 4'b1001;
adder a0(row[0] , row[3] ,size,t[0]); // row[0] + row[3] = t[0]
adder a1(row[1] , row[2] ,size,t[1]); // row[1] + row[2] = t[1]
// 2's complement representation for -row[2] and -row[3].
assign temp_input[0] = (~row[2])+11'b000_0000_0001;
assign temp_input[1] = (~row[3])+11'b000_0000_0001;
adder a2(row[1] , temp_input[0],size,t[2]); //row[1]-row[2] = t[2]
adder a3(row[0] , temp_input[1],size,t[3]); // row[0] - row[3] =t[3]
// The above four adders are used for computing the stage-1
//of the butterfly
// The below adders will perform stage-2 operation
assign size = 4'b1010;
adder a4(t[0] , t[1] , size , temp_result[0]);
assign result = temp_result[0]; // t[0] + t[1] = result[0]
assign temp_input[0] = (~t[1])+11'b0_0000_0001;
adder a5(t[0] ,temp_input[1],size, temp_result[1]);
assign result[2] = temp_result[1]; // t[0] - t[1] = result[2]
assign temp_input[1] = t[3]<<1; // left shifts the t[3] = 2t[3]
adder a6(t[2] , temp_input[1], size , temp_result[0]); // computes the addition
assign result[1] = temp_result[2]; // 2t[3] + t[2] = result[1]
assign temp_input[1] = t[2]<<1; // left shifts the t[2] = 2t[2]
assign temp_input[1] = (~temp_input[1])+11'b0_0000_0001;
//computes the 2's complement of -2t[2]
adder a7(t[3] , temp_input[0], size , temp_result[0]); // computes the addition
assign result[3] = temp_result[3]; // t[3] -2t[2] = result[3]
endmodule
This is the error i got when i run this in model sim
* Error: D:/Integer Transform block/butterfly.v(2): (vlog-2110) Illegal reference to net array "row".
# ** Error: D:/Integer Transform block/butterfly.v(2): (vlog-2110) Illegal reference to net array "result".
# ** Error: D:/Integer Transform block/butterfly.v(39): (vlog-2110) Illegal reference to net array "result".
# ** Error: D:/Integer Transform block/butterfly.v(39): Cannot assign a packed type to an unpacked type
Please explain me how to code for these kind of inputs and outputs
Thanks and Regards
Deepak
Hello friends,
I am facing some problem with the code. I am implementing a algorithm in verilog. The code below i pasted is a butterfly code.
The inputs to the butterfly are 4 words each of 12bits..
The outputs to the butterfly are 4 words each of 14 bits.
`include "adder.v"
module butterfly(row , result);
input [9:0]row[3:0];
output[10:0]result[3:0];
wire [10:0]t[3:0];
wire [11:0]temp_result[3:0];
wire [11:0]temp_input[1:0];
wire [3:0] size;
assign size = 4'b1001;
adder a0(row[0] , row[3] ,size,t[0]); // row[0] + row[3] = t[0]
adder a1(row[1] , row[2] ,size,t[1]); // row[1] + row[2] = t[1]
// 2's complement representation for -row[2] and -row[3].
assign temp_input[0] = (~row[2])+11'b000_0000_0001;
assign temp_input[1] = (~row[3])+11'b000_0000_0001;
adder a2(row[1] , temp_input[0],size,t[2]); //row[1]-row[2] = t[2]
adder a3(row[0] , temp_input[1],size,t[3]); // row[0] - row[3] =t[3]
// The above four adders are used for computing the stage-1
//of the butterfly
// The below adders will perform stage-2 operation
assign size = 4'b1010;
adder a4(t[0] , t[1] , size , temp_result[0]);
assign result = temp_result[0]; // t[0] + t[1] = result[0]
assign temp_input[0] = (~t[1])+11'b0_0000_0001;
adder a5(t[0] ,temp_input[1],size, temp_result[1]);
assign result[2] = temp_result[1]; // t[0] - t[1] = result[2]
assign temp_input[1] = t[3]<<1; // left shifts the t[3] = 2t[3]
adder a6(t[2] , temp_input[1], size , temp_result[0]); // computes the addition
assign result[1] = temp_result[2]; // 2t[3] + t[2] = result[1]
assign temp_input[1] = t[2]<<1; // left shifts the t[2] = 2t[2]
assign temp_input[1] = (~temp_input[1])+11'b0_0000_0001;
//computes the 2's complement of -2t[2]
adder a7(t[3] , temp_input[0], size , temp_result[0]); // computes the addition
assign result[3] = temp_result[3]; // t[3] -2t[2] = result[3]
endmodule
This is the error i got when i run this in model sim
* Error: D:/Integer Transform block/butterfly.v(2): (vlog-2110) Illegal reference to net array "row".
# ** Error: D:/Integer Transform block/butterfly.v(2): (vlog-2110) Illegal reference to net array "result".
# ** Error: D:/Integer Transform block/butterfly.v(39): (vlog-2110) Illegal reference to net array "result".
# ** Error: D:/Integer Transform block/butterfly.v(39): Cannot assign a packed type to an unpacked type
Please explain me how to code for these kind of inputs and outputs
Thanks and Regards
Deepak