Modelsim Simulation Problem

entity packfinder is
Port ( pfind_bus : in STD_LOGIC_VECTOR (6 downto 0);
pfind_clk: in STD_LOGIC;
-- pfind_mode : in STD_LOGIC;
pfind_rst : in STD_LOGIC;
pfind_start: out STD_LOGIC;
pfind_dataout: out STD_LOGIC_VECTOR(6 downto 0)
);
end packfinder;

architecture Behavioral of packfinder is
signal databuffer: STD_LOGIC_VECTOR(6 downto 0);
signal startPack: STD_LOGIC;
begin

process(pfind_clk, pfind_rst)
begin
if pfind_rst='1' then
startPack <= '0';
databuffer <= (others=>'0');
pfind_dataout<=databuffer;
pfind_start <='0';

else
if rising_edge(pfind_clk) then

databuffer<=pfind_bus;

if(startPack ='1') then
pfind_dataout <=databuffer;
pfind_start <='1';
else
pfind_start <='0';

if( (databuffer(6)='0') and
(databuffer(3)='0') and
(databuffer(2)='1') and
(databuffer(1)='0') and
(databuffer(0)='1') ) then

pfind_start <='1'; -- make it start the next clock
pfind_dataout <=databuffer;
startPack<='1';

end if;
end if;


end if; -- if rising

end if; -- if rst
end process;

end Behavioral;

Click to expand...

Inst_packfinder: packfinder PORT MAP(
pfind_bus => top_bus,
pfind_clk => clk0X, -- sampling clock
pfind_rst => top_rst,
pfind_start => pfindsam,
pfind_dataout => datacon2
);
test<= pfindsam;

Click to expand...