kzirshan
Newbie level 2
difference b/w serial and parallel communication
hie
m working on AES encryptor project, i have designed RTL core of the AES encryptor in verilog HDL and chkd it's validity by simulating it, now i am intrested to check response of core by configure the FPGA and by interfacing FPGA to the PC.
The Pc will send data to the FPGA the FPGA will perform encryption and send it back to the PC......
your help is required to interface the PC with the FPGA for the communication,kindly help me in this regard, suggest some documents,web address or book, which can help me in this regard.
regards
kzirshan
hie
m working on AES encryptor project, i have designed RTL core of the AES encryptor in verilog HDL and chkd it's validity by simulating it, now i am intrested to check response of core by configure the FPGA and by interfacing FPGA to the PC.
The Pc will send data to the FPGA the FPGA will perform encryption and send it back to the PC......
your help is required to interface the PC with the FPGA for the communication,kindly help me in this regard, suggest some documents,web address or book, which can help me in this regard.
regards
kzirshan