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  1. #1
    Newbie level 2
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    difference b/w serial and parallel communication

    hie

    m working on AES encryptor project, i have designed RTL core of the AES encryptor in verilog HDL and chkd it's validity by simulating it, now i am intrested to check response of core by configure the FPGA and by interfacing FPGA to the PC.
    The Pc will send data to the FPGA the FPGA will perform encryption and send it back to the PC......
    your help is required to interface the PC with the FPGA for the communication,kindly help me in this regard, suggest some documents,web address or book, which can help me in this regard.

    regards
    kzirshan

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  2. #2
    Advanced Member level 2
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    pc fpga communication

    There are some options, the one a bit easier to implement than the other:
    1. easiest
    build a top level that includes a uart Tx/Rx and build a simple rs232 communication protocol on the PC

    2. moderate
    same as above but using USB

    3. difficult
    include a ethernet mac/phy in the fpga
    poll the fpga board through ethernet connection from PC

    if it is your only intention to test the core, I would recommend the first solution.
    guaranteed to work, easy to implement, quick and dirty testing possible

    good luck



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