cherjier
Member level 5
Hi, i have do a simple templete as a reference for the discussion.
what do u guys think we should do to constraints the clock properly?
Bese on my point of view, all input clock need to constraints using period constraints. Since "clk_internal_a" is derive by the dcm, ISE will generate auto constraints the "clk_internal_a" and "clk_gate_internal_a".
as for the example above, some FF are clock by "clk_internal_a" and "clk_gate_internal_a",do u constraints this path using to:from constraints since it using a bufgmux for xilinx? what if some register are clock at negative edge?
besides, there is a CDC path. basically i will set it to false path but recently i have read some document mention that this path should set it to a fast/slow path instead of false path. my doubt is how to determine the net delay for fast/slow path?
what do u guys think we should do to constraints the clock properly?
Code:
module clk_discussion (
clk_a, //assume 12MHz
clk_b, //assume 40MHz
rst_n,
.
.
.
);
input clk_a, clk_b, rst_n;
reg a,b,clk_gate_sel;
dcm dcm_u0 (
//DCM
.clk_in (clk_a),
.clk_fx (clk_internal_a), //assume 32MHz
.
.
.
);
clk_gate clk_gate_u0 (
//bufgmux
.I0 (clk_internal_a),
.I1 (1'b0),
.O (clk_gate_internal_a),
.S (clk_gate_sel)
);
always @(posedge clk_internal_a or ....)
if(!rst_n)
a <= 1'b0;
else
a <= .....
always @(posedge clk_gate_internal_a or ...)
if(!rst_n)
b <= 1'b0;
else
b <= a;
// 2 ff synchronizer
sync sync_u0 (
.in (b),
.out (c),
.clk (clk_b),
.rst_n (rst_n)
);
always @(posedge clk_b)
if (!rst_n)
d <= 1'b0;
else
d <= c;
endmoduleBese on my point of view, all input clock need to constraints using period constraints. Since "clk_internal_a" is derive by the dcm, ISE will generate auto constraints the "clk_internal_a" and "clk_gate_internal_a".
as for the example above, some FF are clock by "clk_internal_a" and "clk_gate_internal_a",do u constraints this path using to:from constraints since it using a bufgmux for xilinx? what if some register are clock at negative edge?
besides, there is a CDC path. basically i will set it to false path but recently i have read some document mention that this path should set it to a fast/slow path instead of false path. my doubt is how to determine the net delay for fast/slow path?