Video controller IP project

cpld video controller

Well... i have already finished doing my IP project. Purpose is, to create video controller IP, which may be reused in EDK. I am doing everything on the XUPV2P board. My video controller IP has Asynchronous FIFO module built in it. i have already connected it to the EDK as custom peripheral. I can even latch some RGB data with software, and fill the screen with any color!

what i did next is... i added CompactFLASH peripheral from Xilinx... and now i read the BMP images from the CF card, and store them on the DDR memory... now, i want to display data from the DDR on my video controller!

there is such a project on the Digilent website...but they use already made controller in Verilog, which is 640x480. Mine is 1024x768, in VHDL and with Asynchronous FIFO design.

problem is...when i try to read pixture byte by byte...it is not being displayed...it is displayed like some mess....a lot of lines etc...

i think the problem is in speed...or maybe in the correct data latching on to the PLB bus...

any suggestions?

fpga video controller project

ok..as i see noone could help anyhow..

is there at least anyone who is experimenting with the XUPV2P board now?

lets do something together! i already have written VHDL code, and succeffully runned it inside the EDK as a peripheral... i need someone else who is interested in the video projects, so that we could finish the job together! we will not start from scratch! is there any such person?