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Synthesis Error - Spartan 3E

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Zhane

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When I tried to assign CLK to all of my port maps clk in top.prj ... i get alot of errors and warning as follows:

Reading design: top.prj

=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "D:/Xilinx/Projects/TPM/sampling.vhd" in Library work.
Architecture behavioral of Entity sampling is up to date.
Compiling vhdl file "D:/Xilinx/Projects/TPM/clkmaker.vhd" in Library work.
Architecture behavioral of Entity clkmaker is up to date.
Compiling vhdl file "D:/Xilinx/Projects/TPM/samplepack.vhd" in Library work.
Architecture behavioral of Entity samplepack is up to date.
Compiling vhdl file "D:/Xilinx/Projects/TPM/transmitter.vhd" in Library work.
Architecture txd_arch of Entity transmitter is up to date.
Compiling vhdl file "D:/Xilinx/Projects/TPM/top.vhd" in Library work.
Entity <top> compiled.
Entity <top> (Architecture <behavioral>) compiled.

=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <top> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <clkmaker> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <samplepack> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <transmitter> in library <work> (architecture <txd_arch>).

Analyzing hierarchy for entity <sampling> in library <work> (architecture <behavioral>).


=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <top> in library <work> (Architecture <behavioral>).
WARNING:Xst:753 - "D:/Xilinx/Projects/TPM/top.vhd" line 86: Unconnected output port 'CLKIN_IBUFG_OUT' of component 'clkmaker'.
WARNING:Xst:753 - "D:/Xilinx/Projects/TPM/top.vhd" line 86: Unconnected output port 'LOCKED_OUT' of component 'clkmaker'.
Entity <top> analyzed. Unit <top> generated.

Analyzing Entity <clkmaker> in library <work> (Architecture <behavioral>).
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <CLKIN_IBUFG_INST> in unit <clkmaker>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <CLKIN_IBUFG_INST> in unit <clkmaker>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <CLKIN_IBUFG_INST> in unit <clkmaker>.
Set user-defined property "PHASE_SHIFT = 0" for instance <DCM_SP_INST> in unit <clkmaker>.
Set user-defined property "CLK_FEEDBACK = 1X" for instance <DCM_SP_INST> in unit <clkmaker>.
Set user-defined property "CLKDV_DIVIDE = 2.0000000000000000" for instance <DCM_SP_INST> in unit <clkmaker>.
Set user-defined property "CLKFX_DIVIDE = 1" for instance <DCM_SP_INST> in unit <clkmaker>.
Set user-defined property "CLKFX_MULTIPLY = 3" for instance <DCM_SP_INST> in unit <clkmaker>.
Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance <DCM_SP_INST> in unit <clkmaker>.
Set user-defined property "CLKIN_PERIOD = 30.3030000000000010" for instance <DCM_SP_INST> in unit <clkmaker>.
Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance <DCM_SP_INST> in unit <clkmaker>.
Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance <DCM_SP_INST> in unit <clkmaker>.
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance <DCM_SP_INST> in unit <clkmaker>.
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance <DCM_SP_INST> in unit <clkmaker>.
Set user-defined property "DSS_MODE = NONE" for instance <DCM_SP_INST> in unit <clkmaker>.
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance <DCM_SP_INST> in unit <clkmaker>.
Set user-defined property "FACTORY_JF = C080" for instance <DCM_SP_INST> in unit <clkmaker>.
Set user-defined property "STARTUP_WAIT = FALSE" for instance <DCM_SP_INST> in unit <clkmaker>.
Entity <clkmaker> analyzed. Unit <clkmaker> generated.

Analyzing Entity <samplepack> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 - "D:/Xilinx/Projects/TPM/samplepack.vhd" line 68: The following signals are missing in the process sensitivity list:
statusrdy, samplecnt, samplebuff, rawcnt, rawbuff.
Entity <samplepack> analyzed. Unit <samplepack> generated.

Analyzing Entity <sampling> in library <work> (Architecture <behavioral>).
INFO:Xst:1432 - Contents of array
  1. may be accessed with a negative index, causing simulation mismatch.
    INFO:Xst:1433 - Contents of array
    1. may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
      WARNING:Xst:790 - "D:/Xilinx/Projects/TPM/sampling.vhd" line 90: Index value(s) does not match array range, simulation mismatch.
      WARNING:Xst:790 - "D:/Xilinx/Projects/TPM/sampling.vhd" line 90: Index value(s) does not match array range, simulation mismatch.
      WARNING:Xst:790 - "D:/Xilinx/Projects/TPM/sampling.vhd" line 101: Index value(s) does not match array range, simulation mismatch.
      INFO:Xst:1432 - Contents of array
      1. may be accessed with a negative index, causing simulation mismatch.
        INFO:Xst:1433 - Contents of array
        1. may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
          Entity <sampling> analyzed. Unit <sampling> generated.

          Analyzing Entity <transmitter> in library <work> (Architecture <txd_arch>).
          Entity <transmitter> analyzed. Unit <transmitter> generated.


          =========================================================================
          * HDL Synthesis *
          =========================================================================

          Performing bidirectional port resolution...

          Synthesizing Unit <transmitter>.
          Related source file is "D:/Xilinx/Projects/TPM/transmitter.vhd".
          WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
          Found 1-bit register for signal <busyTxD>.
          Found 1-bit register for signal <TxD>.
          Found 8-bit register for signal <dataBuffer>.
          Found 26-bit up accumulator for signal <phaseAcc>.
          Found 4-bit register for signal <state>.
          Found 4-bit adder for signal <state$addsub0000> created at line 81.
          Found 4-bit comparator greatequal for signal <state$cmp_ge0000> created at line 77.
          Found 4-bit comparator lessequal for signal <state$cmp_le0000> created at line 77.
          Found 4-bit comparator greater for signal <TxD$cmp_gt0000> created at line 77.
          Found 4-bit comparator less for signal <TxD$cmp_lt0000> created at line 77.
          Summary:
          inferred 1 Accumulator(s).
          inferred 14 D-type flip-flop(s).
          inferred 1 Adder/Subtractor(s).
          inferred 4 Comparator(s).
          Unit <transmitter> synthesized.


          Synthesizing Unit <sampling>.
          Related source file is "D:/Xilinx/Projects/TPM/sampling.vhd".
          WARNING:Xst:647 - Input <input<6:4>> is never used.
          WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
          WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
          WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
          Found 1-bit register for signal <error>.
          Found 4-bit register for signal <rawdata>.
          Found 4-bit register for signal <sampleddata>.
          Found 1-bit register for signal <ready>.
          Found 4-bit 5-to-1 multiplexer for signal <$varindex0000> created at line 101.
          Found 2-bit adder carry out for signal <count$addsub0000> created at line 81.
          Found 32-bit 4-to-1 multiplexer for signal <count$mux0001> created at line 90.
          Found 2-bit adder for signal <count_0$addsub0000> created at line 81.
          Found 2-bit adder carry out for signal <count_0$addsub0002> created at line 81.
          Found 2-bit adder for signal <count_1$add0000> created at line 81.
          Found 2-bit adder for signal <count_1$addsub0000> created at line 81.
          Found 1-bit adder carry out for signal <count_1$addsub0002> created at line 81.
          Found 2-bit adder carry out for signal <count_1$addsub0003> created at line 81.
          Found 4-bit comparator equal for signal <count_1$cmp_eq0000> created at line 80.
          Found 2-bit adder for signal <count_2$add0001> created at line 81.
          Found 1-bit adder carry out for signal <count_2$addsub0002> created at line 81.
          Found 2-bit adder carry out for signal <count_2$addsub0003> created at line 81.
          Found 4-bit comparator equal for signal <count_2$cmp_eq0000> created at line 80.
          Found 4-bit comparator equal for signal <count_2$cmp_eq0001> created at line 80.
          Found 2-bit adder for signal <count_3$addsub0001> created at line 81.
          Found 1-bit adder carry out for signal <count_3$addsub0002> created at line 81.
          Found 4-bit comparator equal for signal <count_3$cmp_eq0000> created at line 80.
          Found 4-bit comparator equal for signal <count_3$cmp_eq0001> created at line 80.
          Found 4-bit comparator equal for signal <count_3$cmp_eq0002> created at line 80.
          Found 32-bit up counter for signal <counter>.
          Found 32-bit comparator greater for signal <index$cmp_gt0000> created at line 90.
          Found 3-bit comparator greater for signal <index$cmp_gt0001> created at line 90.
          Found 32-bit comparator greater for signal <index$cmp_gt0002> created at line 90.
          Found 20-bit register for signal
          1. .
            Summary:
            inferred 1 Counter(s).
            inferred 30 D-type flip-flop(s).
            inferred 12 Adder/Subtractor(s).
            inferred 9 Comparator(s).
            inferred 36 Multiplexer(s).
            Unit <sampling> synthesized.


            Synthesizing Unit <clkmaker>.
            Related source file is "D:/Xilinx/Projects/TPM/clkmaker.vhd".
            Unit <clkmaker> synthesized.


            Synthesizing Unit <samplepack>.
            Related source file is "D:/Xilinx/Projects/TPM/samplepack.vhd".
            WARNING:Xst:646 - Signal <statuserror> is assigned but never used.
            WARNING:Xst:737 - Found 1-bit latch for signal <OUTPUTRAW_5>.
            WARNING:Xst:737 - Found 1-bit latch for signal <OUTPUTRAW_6>.
            WARNING:Xst:737 - Found 1-bit latch for signal <OUTPUTRAW_7>.
            WARNING:Xst:737 - Found 1-bit latch for signal <samplecnt>.
            WARNING:Xst:737 - Found 1-bit latch for signal <OUTPUTSAM_0>.
            WARNING:Xst:737 - Found 1-bit latch for signal <OUTPUTSAM_1>.
            WARNING:Xst:737 - Found 1-bit latch for signal <OUTPUTSAM_2>.
            WARNING:Xst:737 - Found 1-bit latch for signal <OUTPUTSAM_3>.
            WARNING:Xst:737 - Found 1-bit latch for signal <OUTPUTSAM_4>.
            WARNING:Xst:737 - Found 1-bit latch for signal <OUTPUTSAM_5>.
            WARNING:Xst:737 - Found 1-bit latch for signal <OUTPUTSAM_6>.
            WARNING:Xst:737 - Found 1-bit latch for signal <OUTPUTSAM_7>.
            WARNING:Xst:737 - Found 1-bit latch for signal <SREADY>.
            WARNING:Xst:737 - Found 1-bit latch for signal <OUTPUTRAW_0>.
            WARNING:Xst:737 - Found 1-bit latch for signal <OUTPUTRAW_1>.
            WARNING:Xst:737 - Found 1-bit latch for signal <OUTPUTRAW_2>.
            WARNING:Xst:737 - Found 1-bit latch for signal <OUTPUTRAW_3>.
            WARNING:Xst:737 - Found 1-bit latch for signal <OUTPUTRAW_4>.
            Unit <samplepack> synthesized.


            Synthesizing Unit <top>.
            Related source file is "D:/Xilinx/Projects/TPM/top.vhd".
            WARNING:Xst:647 - Input <RxD> is never used.
            WARNING:Xst:1780 - Signal <idleRxD> is never used or assigned.
            WARNING:Xst:1780 - Signal <startTxD> is never used or assigned.
            WARNING:Xst:646 - Signal <busyTxD> is assigned but never used.
            WARNING:Xst:646 - Signal <SAMPLECLK> is assigned but never used.
            WARNING:Xst:646 - Signal <CLKCLK> is assigned but never used.
            WARNING:Xst:646 - Signal <RREADY> is assigned but never used.
            WARNING:Xst:646 - Signal <SREADY> is assigned but never used.
            WARNING:Xst:646 - Signal <BUFFERRAW> is assigned but never used.
            WARNING:Xst:653 - Signal <ready> is used but never assigned. Tied to value 0.
            WARNING:Xst:646 - Signal <BUFFERSAM> is assigned but never used.
            WARNING:Xst:653 - Signal <data> is used but never assigned. Tied to value 00000000.
            Unit <top> synthesized.


            =========================================================================
            HDL Synthesis Report

            Macro Statistics
            # Adders/Subtractors : 13
            1-bit adder carry out : 3
            2-bit adder : 5
            2-bit adder carry out : 4
            4-bit adder : 1
            # Counters : 1
            32-bit up counter : 1
            # Accumulators : 1
            26-bit up accumulator : 1
            # Registers : 13
            1-bit register : 4
            4-bit register : 8
            8-bit register : 1
            # Latches : 18
            1-bit latch : 18
            # Comparators : 13
            3-bit comparator greater : 1
            32-bit comparator greater : 2
            4-bit comparator equal : 6
            4-bit comparator greatequal : 1
            4-bit comparator greater : 1
            4-bit comparator less : 1
            4-bit comparator lessequal : 1
            # Multiplexers : 2
            32-bit 4-to-1 multiplexer : 1
            4-bit 5-to-1 multiplexer : 1

            =========================================================================

            =========================================================================
            * Advanced HDL Synthesis *
            =========================================================================

            Loading device for application Rf_Device from file '3s500e.nph' in environment D:\Xilinx.
            WARNING:Xst:1710 - FF/Latch <dataBuffer_0> (without init value) has a constant value of 0 in block <TxD_portmap>.
            WARNING:Xst:1710 - FF/Latch <dataBuffer_1> (without init value) has a constant value of 0 in block <TxD_portmap>.
            WARNING:Xst:1710 - FF/Latch <dataBuffer_2> (without init value) has a constant value of 0 in block <TxD_portmap>.
            WARNING:Xst:1710 - FF/Latch <dataBuffer_3> (without init value) has a constant value of 0 in block <TxD_portmap>.
            WARNING:Xst:1710 - FF/Latch <dataBuffer_4> (without init value) has a constant value of 0 in block <TxD_portmap>.
            WARNING:Xst:1710 - FF/Latch <dataBuffer_5> (without init value) has a constant value of 0 in block <TxD_portmap>.
            WARNING:Xst:1710 - FF/Latch <dataBuffer_6> (without init value) has a constant value of 0 in block <TxD_portmap>.
            WARNING:Xst:1710 - FF/Latch <dataBuffer_7> (without init value) has a constant value of 0 in block <TxD_portmap>.
            WARNING:Xst:2677 - Node <ready> of sequential type is unconnected in block <Inst_sampling>.
            WARNING:Xst:2677 - Node <rawdata_0> of sequential type is unconnected in block <Inst_sampling>.
            WARNING:Xst:2677 - Node <rawdata_1> of sequential type is unconnected in block <Inst_sampling>.
            WARNING:Xst:2677 - Node <rawdata_2> of sequential type is unconnected in block <Inst_sampling>.
            WARNING:Xst:2677 - Node <rawdata_3> of sequential type is unconnected in block <Inst_sampling>.
            WARNING:Xst:2677 - Node <error> of sequential type is unconnected in block <Inst_sampling>.
            WARNING:Xst:2677 - Node <sampleddata_0> of sequential type is unconnected in block <Inst_sampling>.
            WARNING:Xst:2677 - Node <sampleddata_1> of sequential type is unconnected in block <Inst_sampling>.
            WARNING:Xst:2677 - Node <sampleddata_2> of sequential type is unconnected in block <Inst_sampling>.
            WARNING:Xst:2677 - Node <sampleddata_3> of sequential type is unconnected in block <Inst_sampling>.
            WARNING:Xst:2677 - Node <busyTxD> of sequential type is unconnected in block <TxD_portmap>.

            =========================================================================
            Advanced HDL Synthesis Report

            Macro Statistics
            # Adders/Subtractors : 13
            1-bit adder carry out : 3
            2-bit adder : 5
            2-bit adder carry out : 4
            4-bit adder : 1
            # Counters : 1
            32-bit up counter : 1
            # Accumulators : 1
            26-bit up accumulator : 1
            # Registers : 44
            Flip-Flops : 44
            # Latches : 18
            1-bit latch : 18
            # Comparators : 13
            3-bit comparator greater : 1
            32-bit comparator greater : 2
            4-bit comparator equal : 6
            4-bit comparator greatequal : 1
            4-bit comparator greater : 1
            4-bit comparator less : 1
            4-bit comparator lessequal : 1
            # Multiplexers : 2
            32-bit 4-to-1 multiplexer : 1
            4-bit 5-to-1 multiplexer : 1

            =========================================================================

            =========================================================================
            * Low Level Synthesis *
            =========================================================================
            INFO:Xst:2261 - The FF/Latch <dataBuffer_0> in Unit <transmitter> is equivalent to the following 7 FFs/Latches, which will be removed : <dataBuffer_1> <dataBuffer_2> <dataBuffer_3> <dataBuffer_4> <dataBuffer_5> <dataBuffer_6> <dataBuffer_7>
            WARNING:Xst:1710 - FF/Latch <dataBuffer_0> (without init value) has a constant value of 0 in block <transmitter>.
            WARNING:Xst:2677 - Node
            1. of sequential type is unconnected in block <sampling>.
              WARNING:Xst:2677 - Node
              1. of sequential type is unconnected in block <sampling>.
                WARNING:Xst:2677 - Node
                1. of sequential type is unconnected in block <sampling>.
                  WARNING:Xst:2677 - Node
                  1. of sequential type is unconnected in block <sampling>.
                    WARNING:Xst:2170 - Unit samplepack : the following signal(s) form a combinatorial loop: RREADY.
                    WARNING:Xst:2016 - Found a loop when searching source clock on port '_n0000:_n0000'
                    Last warning will be issued only once.

                    Optimizing unit <top> ...

                    Optimizing unit <transmitter> ...

                    Optimizing unit <sampling> ...

                    Optimizing unit <samplepack> ...
                    WARNING:Xst:2677 - Node <TxD_portmap/busyTxD> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/ready> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/rawdata_0> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/rawdata_1> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/rawdata_2> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/rawdata_3> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/error> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/oldsample_3_0> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/oldsample_3_1> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/oldsample_3_2> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/oldsample_3_3> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/oldsample_2_0> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/oldsample_2_1> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/oldsample_2_2> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/oldsample_2_3> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/oldsample_1_0> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/oldsample_1_1> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/oldsample_1_2> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/oldsample_1_3> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/oldsample_0_0> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/oldsample_0_1> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/oldsample_0_2> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/oldsample_0_3> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/sampleddata_0> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/sampleddata_1> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/sampleddata_2> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/sampleddata_3> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_0> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_1> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_2> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_3> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_4> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_5> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_6> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_7> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_8> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_9> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_10> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_11> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_12> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_13> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_14> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_15> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_16> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_17> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_18> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_19> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_20> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_21> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_22> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_23> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_24> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_25> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_26> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_27> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_28> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_29> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_30> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/Inst_sampling/counter_31> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/OUTPUTRAW_5> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/OUTPUTRAW_6> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/OUTPUTRAW_7> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/OUTPUTRAW_4> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/samplecnt> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/SREADY> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/OUTPUTRAW_0> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/OUTPUTRAW_1> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/OUTPUTRAW_2> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/OUTPUTRAW_3> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/OUTPUTSAM_0> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/OUTPUTSAM_1> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/OUTPUTSAM_2> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/OUTPUTSAM_3> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/OUTPUTSAM_4> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/OUTPUTSAM_5> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/OUTPUTSAM_6> of sequential type is unconnected in block <top>.
                    WARNING:Xst:2677 - Node <Inst_samplepack/OUTPUTSAM_7> of sequential type is unconnected in block <top>.

                    Mapping all equations...
                    ERROR:Xst:2035 - Port <CLK> has illegal connection. Port is connected to input buffer and following ports:
                    Port <C> of node <TxD_portmap/phaseAcc_0> (FD) in unit <top>
                    Port <C> of node <TxD_portmap/phaseAcc_1> (FD) in unit <top>
                    Port <C> of node <TxD_portmap/phaseAcc_2> (FD) in unit <top>
                    Port <C> of node <TxD_portmap/phaseAcc_3> (FD) in unit <top>
                    Port <C> of node <TxD_portmap/phaseAcc_4> (FD) in unit <top>
                    Port <C> of node <TxD_portmap/phaseAcc_5> (FD) in unit <top>
                    Port <C> of node <TxD_portmap/phaseAcc_6> (FD) in unit <top>
                    Port <C> of node <TxD_portmap/phaseAcc_7> (FD) in unit <top>
                    Port <C> of node <TxD_portmap/phaseAcc_8> (FD) in unit <top>
                    Port <C> of node <TxD_portmap/phaseAcc_9> (FD) in unit <top>
                    Port <C> of node <TxD_portmap/phaseAcc_10> (FD) in unit <top>
                    Port <C> of node <TxD_portmap/phaseAcc_11> (FD) in unit <top>
                    Port <C> of node <TxD_portmap/phaseAcc_12> (FD) in unit <top>
                    Port <C> of node <TxD_portmap/phaseAcc_13> (FD) in unit <top>
                    Port <C> of node <TxD_portmap/phaseAcc_14> (FD) in unit <top>
                    Port <C> of node <TxD_portmap/phaseAcc_15> (FD) in unit <top>
                    Port <C> of node <TxD_portmap/phaseAcc_16> (FD) in unit <top>
                    Port <C> of node <TxD_portmap/phaseAcc_17> (FD) in unit <top>
                    Port <C> of node <TxD_portmap/phaseAcc_18> (FD) in unit <top>
                    Port <C> of node <TxD_portmap/phaseAcc_19> (FD) in unit <top>
                    Port <C> of node <TxD_portmap/phaseAcc_20> (FD) in unit <top>
                    Port <C> of node <TxD_portmap/phaseAcc_21> (FD) in unit <top>
                    Port <C> of node <TxD_portmap/phaseAcc_22> (FD) in unit <top>
                    Port <C> of node <TxD_portmap/phaseAcc_23> (FD) in unit <top>
                    Port <C> of node <TxD_portmap/phaseAcc_24> (FD) in unit <top>
                    Port <C> of node <TxD_portmap/phaseAcc_25> (FD) in unit <top>
                    CPU : 11.52 / 11.67 s | Elapsed : 12.00 / 12.00 s

                    -->

                    Total memory usage is 163860 kilobytes

                    Number of errors : 1 ( 0 filtered)
                    Number of warnings : 144 ( 0 filtered)
                    Number of infos : 5 ( 0 filtered)


                    Process "Synthesize" failed
Click to expand...



                  1. what's wrong ah? Can someone enlighten me?
 

i do not know VHDL very well but base on your code,
you have a few module like clkmaker, samplepack, and transmitter.

you have connected the input "CLK" to all of this module. this should be fine but since "CLK" is connected to clkmaker, which is a connected to IBUFG, which is illegal for u to connect "CLK" to other module or FF.

if you want other module running at the same frequency to "CLK", connect "CLK0_OUT" from the clkmaker to other module.

this should solve your synthesize error.
 

Thanks, Im able to synthesize it. But i'm still getting all of those warnings.

It seems that most of the warning come from this file of my coding.. something about the index of oldsample and count isnt quite right. I've cracked my head over it and cant seem to be able to find anything seriously wrong with it.

Any idea what i can do ?

----------------------------------------------------------------------------------

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sampling is
Port ( CLK : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (6 downto 0); -- input channels
sampleddata : out STD_LOGIC_VECTOR(3 downto 0); -- processed data(nibble)
rawdata: OUT STD_LOGIC_VECTOR(3 downto 0); -- raw data(nibble)

-- sampleddat0 : out STD_LOGIC_VECTOR(3 downto 0);
-- sampleddat1 : out STD_LOGIC_VECTOR(3 downto 0);
-- sampleddat2 : out STD_LOGIC_VECTOR(3 downto 0);
-- sampleddat3 : out STD_LOGIC_VECTOR(3 downto 0);
error : out std_logic ; -- indicate when sampled data is all different
ready: OUT std_logic -- indicate data sampled is ready
);
end sampling;

architecture Behavioral of sampling is

subtype data is std_logic_vector(3 downto 0);
type samplearray is array(4 downto 0) of data;
signal oldsample: samplearray;


signal counter: integer:=0;
type vec is array(3 downto 0) of integer;


begin
-- use constants of external clk to calculate sampling rate. eg. how many samples per real clock
-- put counter in process to count. if majority of them is A, then A is the value

process(CLK)

variable index : integer:=0;
variable count: vec:=(0,0,0,0);

begin
--count(0):=0;count(1):=0;count(2):=0;count(3):=0;

if rising_edge(CLK) then


oldsample(counter)<=input(3 downto 0);
rawdata<=input(3 downto 0);

counter<=counter+1;
if (counter=4) then
-- store inputs, count no. of occurences
for n in 0 to 3 loop
for m in 0 to 3 loop
if(oldsample(n)=oldsample(m)) then
count(n):=count(n)+1; -- at least 1 coz will
-- ownself = ownself
end if;
end loop;
end loop;

----- check for repeated most frequently, return index ----
index :=0;
for i in 0 to 3 loop
if( count(i)>count(index) ) then
index := i;
end if;
end loop;
----- check if all different --------------------
if( count(0)=1 and count(1)=1 and count(2)=1 and count(3)=1) then
error<='1'; -- if all different error
end if;
------------------------------------------------


sampleddata<=oldsample(index); -- output most frequent

ready<='1';
counter <= 0;
else
ready<='0';
error<='0';
end if;

-- sampleddat0<=oldsample(0);
-- sampleddat1<=oldsample(1);
-- sampleddat2<=oldsample(2);
-- sampleddat3<=oldsample(3);

end if;

end process;

end Behavioral;
Click to expand...

Added after 55 minutes:

when i try to translate i get this

Applying constraints in "top.ucf" to the design...
ERROR:NgdBuild:756 - "top.ucf" Line 4: Could not find instance(s) 'DCM_SP_INST' in
the design. To suppress this error specify the correct net name or remove
the constraint.
Click to expand...

but my DCP_SP_INST is inside my clkmaker.vhd file

what should I do?
 

for all your warning, it should due to you did not connect the output signal at top level, for example:
WARNING:Xst:2677 - Node <Inst_samplepack/OUTPUTSAM_*> of sequential type is unconnected in block <top>.

refer to your top line 43 and 102, u did not connect the buffersam in top and this will give you a warning shown above. please check your code and make sure it pass the simulation stage.

you may show the detail of your UCF files here.
but for my guess u try this

INST "Inst_clkmaker/DCM_SP_INST" .......
 

hey thanks
it solved my error problem

I've been trying out the following code with TEMPUART.VHD as my top module on my UART. I connected the Uart of my spartan to my PC using a null modem connection.

It's weird cause I never seem to be able to get the data I output , FF and 0A, on my PC. I get 7F instead of FF...

sorry to bother again



for those non-connected ports. if i dont intend to use it yet, will specifying with 'open' works? or is there anyway to make it look connected first?
 

hi Zhane,

sorry, i'm not very familiar with VHDL.

It's weird cause I never seem to be able to get the data I output , FF and 0A, on my PC. I get 7F instead of FF...
Click to expand...

Could it be the transmiter baud rate? check your baud rate is it correct.
and maybe your code did not send a START bit correctly.... u can check your waveform on scope..

for those non-connected ports. if i dont intend to use it yet, will specifying with 'open' works? or is there anyway to make it look connected first?
Click to expand...

for those unconnected port,if it is intentionally left unconnected it should be fine.
if it's a output from a module, u can left it unconnect.
if it's a input to a module, the best is you tide it to 1 or 0, base on the module requirement. just don't let the input port floating.
 

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