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VHDL-AMS error: ADC_REF_LADDER' could not be loaded, entity may requre re-analysis

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linan0827

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Hi everyone!

I am following the Virtuoso AMS Designer Flow to practice the the simulation of the mixed-signal circuits. The simulation project is provided by Cadence, which is vfs_amsflow. When I compile the project all the components in Verilog-AMS is compiled correctly but the only one in VHDL-AMS has a error. The NCVHDL.log indicates the error is

ncvhdl_p: *E:ENNOFN (u/59/59/linan/vfs_amsflow/VFS_AMS_PHY180/adc_ref_ladder/adc_ref_ladder_behav/vhdl.vhms,19|50): Intermidiate file for entity 'ADC_REF_LADDER' could not be loaded, entity may requre re-analysis.
errors:1, warnings: 0
ncvhdl_p: *W,SPUNFW: specific library unit was never processed 'adc_ref_ladder:adc_ref_ladder_behav'.

I have no idea what should I do to fix this problem. Could anyone give me some solution? Thank you very much for your help in advance.

Li Nan
 

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