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Combination of VHDL and Verilog codes?

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vishwa

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verilog codes

Hi,

In a system design, some of the modules are done in VHDL and others in Verilog.

do we get any issues after the integration of the all the modules from both VHDL and Verilog.

Please suggest what to do.


Regards,
Vishwa
 

combination of verilog and vhdl

Mixed language design is quite normal to my opinion. You will notice, that the IP cores supplied from FPGA vendors and third parties often are assembled from mixed language modules. In some cases, even restriction of a HDL language are a reason to use another for some design parts.

As a particular point, mixed language simulation possibly requires additional software licenses, but it is generally supported.When instantiating VHDL modules in Verilog, generics must be defined through old style #( ) syntax instead of defparam, that is unsupported by ModelSim in mixed language.
 

With respect to design : You can easily mix those modules in Verilog and VHDL together if they are related to each other by using Design Compiler ... (1)
With respect to simulation : VCS-MX can support mixed HDL simulation ... (2).
 

Ya...Its True...you will face problem depend on what simulator you going to use

VHDL need order file list
verilog need not order file list

Nc, modelsim , vcs will take care abt it
 

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