Need help in this verilog code

Please tell me in why in my following code delay signal value not getting updated in case of event on strt_bo signal .


`timescale 1ns / 1ps[/b]//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:07:41 06/23/2008
// Design Name:
// Module Name: backof
// Project Name:
// Target Devices:
// Tool versions:
// Description::
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module bcof(rst,xmit_over, strt_bo, strt_def, err1);
input rst;
input xmit_over;
input strt_bo;
output reg strt_def;
output reg err1;

reg [9:0]attempt=0;
reg [9:0]collattempt=0;
reg [9:0]slot_cnt_int;


parameter RUN=1'b1,IDLE=1'b0;


reg [9:0]slot_time=7'b1111111;
//wire [19:0] del;
reg [20:0] delay;
reg temp=0;

reg t1;
wire t2;

assign t2=strt_bo | xmit_over;
//RANDOM NUMBER OUTPUT GENERATION LOGIC
//=======================================
//Note:collattempt is random no. generator output.
always@(posedge strt_bo)
begin
collattempt=collattempt+ 1;
case (collattempt)
0:begin
slot_cnt_int<=0;
delay=slot_cnt_int * slot_time;
end
1:begin
slot_cnt_int<=2;
delay=slot_cnt_int * slot_time;
end
2:begin
slot_cnt_int<=4;
delay=slot_cnt_int * slot_time;
end
3:begin
slot_cnt_int<=8;
delay=slot_cnt_int * slot_time;
end
4:begin
slot_cnt_int<=16;
delay=slot_cnt_int * slot_time;
end
5:begin
slot_cnt_int<=32;
delay=slot_cnt_int * slot_time;
end
6:begin
slot_cnt_int<=64;
delay=slot_cnt_int * slot_time;
end
7:begin
slot_cnt_int<=127;
delay=slot_cnt_int * slot_time;
end
8:begin
slot_cnt_int<=127;
delay=slot_cnt_int * slot_time;
end
9:begin
slot_cnt_int<=127;
delay=slot_cnt_int * slot_time;
end
10:begin
slot_cnt_int<=127;
delay=slot_cnt_int * slot_time;
end
default:begin
slot_cnt_int<=255;
delay=slot_cnt_int * slot_time;
end
endcase
//delay=slot_cnt_int * slot_time;
end
//assign del=slot_cnt_int * slot_time;

always@(t1,temp,delay,rst,attempt,t2,slot_cnt_int)
begin
t1=t2;
if (rst==1)
begin
strt_def=1'b0;
err1=1'b0;
end
else
case(t1)
RUN:
begin
attempt=attempt + 1;
if(attempt==17)
begin
err1=1'b1;
attempt=0;
end
else
begin
while(delay!=0)
begin
temp=temp+1;
delay=delay-1;
end
strt_def=1'b1;
end
end



IDLE:
begin
t1=strt_bo | xmit_over;
end

endcase
end
endmodule

Can you provide a testbench that demonstrates the problem?

I haven't studied your code, but I see a mixture of blocking '=' and non-blocking '<=' assignments. That's usually a bad thing.

The event expression at the beginning of your second 'always' block looks suspicious. Do you really want all those different signals triggering the block? That and the embedded 'while' loop will probably prevent successful synthesis.